Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

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1 Indian Journal of Science and Technology, Vol 9(33), DOI: /ijst/06/v9i33/8985, September 06 ISSN (Print) : ISSN (Online) : Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD J. Vijay Kumar *, B. Naga Raju, M. Vasu Babu, K. Sreelekha 3 and T. Ramanjappa 4 Department of Physics, SKUCET, Sri Krishnadevaraya University, Anantapur , Andhra Pradesh, India; drbnr5@gmail.com, drjvk4@gmail.com Department of Applied Sciences, St. Ann s College of Engineering Technology, Chirala , Andhra Pradesh, India; marellavasu@gmail.com 3 Department of Physics, Government Arts and Science College, Anantapur , Andhra Pradesh, India; sreelekha009@gmail.com 4 Department of Physics, Sri Krishnadevaraya University, Anantapur , Andhra Pradesh, India; thogata@yahoo.com Abstract Background/Objective: Now a day s electronics industry people are concentrating on low power designs. The growing market of portable electronic systems demands microelectronic circuit with ultra low power dissipation. Method: The accomplished operations in this design are logical operations, the arithmetic operations, and branch operations. The outcome values of these operations stored in the registers and they can retrieve from the same when needed. The low power RISC processor with unbiased double precision FPU is designed without any complication, because the power reduction can do in front end technique. Findings: On MAX V CPLD a low power pipelined 64-bit RISC processor is implemented. Arithmetic operations, logical and branch functions of RISC processor are successfully verified with this design. In order to avoid any misbehavior in the jump instructions, the data will flush in the pipeline automatically by the processor architecture. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. Modelsim software is used to verify the simulation results of the design. The ALU operations and double precision floating point arithmetic operation results will be displayed on 7-Segments. Keywords:Altera Max V, CPLD, Low power, Modelsim, RISC. Introduction The low power embedded CPUs industry is altogether dominated by the RISC design technique, since it offers power in small sizes as well. By far embedded CPUs are the largest market for processors. Altogether RISC had led over the market for larger work stations. In the extent, RISC instructions sets have cared for grow in size. Thus, to describe RISC processors some have started using the word load/store, because for all such designs this is the key element. The CPU itself handling many addressing modes, rather the load/store architecture uses a special unit to handle very simple forms of load and store operations. In different fields the floating point operations have found significant applications for the essentials for valuable operation due to its wide range, high precision and easy operation rules. Need to pay attention while designing and doing research on the floating point processing units. It is very simple and expedient to apply the floating point arithmetic in the floating point high-level languages, but it is very tough to implement the arithmetic by hardware 3. Now a day s CPLDs are the best choice for implementing the floating hardware arithmetic *Author for correspondence

2 Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD units, due to their superior consolidation compactness, affordable price, superior execution and adaptable applications essentials for high treasured operation 4. Low power has come out of as a major motif in today s electronics industry. The demand for low power has epitome tilt where power dissolution has become a significant consideration as operation and domain. Now a day s low power embedded processors utilized in ample diversity of applications such as cars, mobile phones, digital cameras, printers, etc. There are lots of techniques like Clock Gating, Supply Voltage Reduction, Multi-Vdd, Dynamic Voltage Frequency Scaling etc to reduce the power 5. In the present work, CPLD based 64-bit RISC processor with a high-speed floating point double precision was executed with the help of pipelined architecture. With this the speed of the operation will increase, in addition overall performance also improved 6. The processor has to implement 4-stage (Fetch, Decode, Execute, Memory Read/Write Back) pipelining including double precision floating point unit. The performed operations in this design are logical operations, the arithmetic operations, and branch operations. The resultant values of these operations will be stored in the registers and they can retrieve from the same when needed. This is a general purpose 64-bit RISC processor with pipelining architecture. Using consecrated buses the processor gets instructions on regular basis to its memory executes all its home-grown instructions in stages with pipelining. It is having 8-bit and 6-bit instructions. 8-bit instructions will use for all arithmetic operations and logical operations. 6-bit instructions will be used for all memory transactions and jump instructions. It will also have specific instructions to approach external ports. In order to avoid any misbehaviour in the jump instructions, the data will flush in the pipeline automatically by the processor architecture 7.. Design Architecture The architecture of the proposed design is shown in Figure. This section presents the design of different modules like IF, ID, RF, EU, FPU, Memory R/W back and IS unit. It also represents low power unit and register block unit. The register block consists of four registers namely R0, R, R, and R3 8.. IF (Instruction Fetch) The instruction fetch consists of the PC (Program Counter) and BP (Branch Prediction). Here the instruction present in the memory will fetch from the PC and stored in the instruction register. The most likely fetched and speculatively executed part is the branch prediction. With this the flow in instruction pipeline will be increased and will carry out the most efficient execution.. ID (Instruction Decoder) The instruction decoder consists of the CU (Control Unit) and register file. From the memory the opcode fetched and for the next steps it will be decoded and Low Power Unit 64-bit REGISTERS IF Module ID Module IE Module Instruc on Branch Predic on PC & Operand Fetch Module (ALU & FPU) Load/Stor e Module PROGRAM MEMORY DATA MEMORY RESULT Figure. Architecture of the proposed design. Indian Journal of Science and Technology

3 J. Vijay Kumar, B. Naga Raju, M. Vasu Babu, K. Sreelekha and T. Ramanjappa go ahead to suitable registers. This can do two concurrent read and one write operation, since it is a two-port register file. Instruction decoder consists of four 64-bit general-purpose registers. If the Reg_write signal is high, then a write operation be executed to the register..3 EU (Execution Unit) This EU consists of the ALU and the ALU control unit. It performs the arithmetic and logical operations and jump or branch instructions. The control unit will offer signals to the ALU and performance of the ALU will depends based on that signals. The double precision floating point operations are also performed by this unit..4 Memory Unit This module will be accessed by the load and store instructions. Finally, the memory access stage is where, if necessary, system memory will be accessed for data, also if write to the data memory is required by the instruction is done in this stage. In order to avoid additional complications it is assumed that a single read or write is accomplished within a single CPU clock cycle..5 Low Power Unit Global clock will serves as the input and gated clock will work as output to the low power unit 9. During the following specific instructions the module will block the main clock. They are. Halt instruction,. Continuous NOP, 3. PC fails to increment. 3. Hardware and Software details Application designers will configure the CPLDs to enforce digital hardware such as mobile phones. CPLDs are another way to extend density of the simple PLDs. The concept is to have a few functional blocks or PLD blocks or macro cells on a single device with general purpose interconnect in between. The macrocell is the building block of CPLD. This macrocell consists of specific logic operations and logic implementing disjunctive normal form expressions. CPLD s are ideal for critical, high-performance control applications, because of their inevitable timing characteristics 0. When compared to FPGAs and other programmable logic devices CPLDs have a shorter and more predictable delay. CPLDs are inexpensive and need relatively small amounts of power; they are frequently used in cost-effective, battery-operated portable applications. The CPLD device used in the present work is MAX V (5M0Z) manufactured by Altera. When compared to other competitive CPLDs, MAX V offers less in cost, consumes less power and provides more I/O pins. MAX V CPLDs have non-volatile architecture and one of the industry s largest densities. Many functions such as flash, RAM, oscillators, and phase-locked loops are integrated within the MAX V. With help of green packaging technology, MAX V has the packages as small as 0 mm. MAX V CPLDs were supported by Quartus II software v.0., which allows productivity enhancements resulting in faster simulation, faster board bring-up, and faster timing closure. The design can be implemented on different nano-chips for better efficiency depending upon the design requirement. 4. Results and Discussion A low power pipelined 64-bit RISC processor with unbiased FPU has compelled on MAX V CPLD. Different operations like arithmetic operations, branch operations and logical functions are proved true on this design. When branch instructions take place as it is compelled using dynamic branch prediction then pipelining would not flow freely. When the processor is idle, CLOCK is switched off through sleep mode by using low power technique. This technique can be adopted to enhance the battery life of the devices. This design can use up only one instruction; however 3-bit RISC processor consumes more than one instruction. This design can put into service in many applications which includes graphics, signal processing and medical equipments. Low power unit simulation results have shown in Figure. The simulation results of 64-bit RISC processor with FPU have shown in Figure 3. Figure 4 shows the RTL schematic view of the processor which describes how the logic resources were organized inside the top-level schematic view. Figure. Simulation result of low power unit. Indian Journal of Science and Technology 3

Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD Figure 3. Simulation result of 64-bit RISC processor with FPU. Figure 4. RTL schematic view of proposed processor.

=64 b_0_00_00_00 _0_0_00 _0_000_000_00 _0000_000_0_000 Table.

4 Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD Figure 3. Simulation result of 64-bit RISC processor with FPU. Figure 4. RTL schematic view of proposed processor. Table shows the results of the RISC processor which performs ALU operations for binary and hexadecimal values Input var (Src) =64 b00_0_00_000 00_00_0 _0_00_0_000 _000_0000_00_0000 Input var (Dst) =64 b_0_00_00_00 _0_0_00 _0_000_000_00 _0000_000_0_000 Table. Results for ALU operations Opcode ALU operation Output in Binary Addition _00_00_00 0_000_000_0 _ _000_000_ 00_ Subtraction 00_0000_00 _00_0_00 _00_00 0_00_0 00_0_000_ 0_ Logical AND 00_0_000 _0000_00_00 0_000_000_0 _000_0000_0 00_0000_0000_ 000_ Logical NOT 00_000_00 _0_0000_0 0_00_000_0 00_00_000_ 0_0 00_ Logical NAND 00_000_0 00_0 _0_0_0 00_0 0 0_ Logical NOR 0000_000_000 _000_0000_000 0_0000_0000_0 00_00_0000_ 00_0_0_ 0000_ Increment 00_0_00 _ _00_0_0 _00_0_0 00_000_0000_ 00_ Division 0000_0000_0000 _0000_0000_000 0_0000_0000_00 00_0000_0000_0 000_0000_0000_ 0000_ Multiplication 00_00_000 00_0 _00_000_ _ Logical XOR 00_0000_00 _0_00_0 _0_0_00 00_ _000_000_ 0_ Logical XNOR _000_00_00 0_000_000 0_0000_ 0_0_0_ 000_0 4 Indian Journal of Science and Technology

5 J. Vijay Kumar, B. Naga Raju, M. Vasu Babu, K. Sreelekha and T. Ramanjappa Logical OR _0_0 _0 0 _00 0 0_000_ Decrement 00_0_00 _ _00_0_0 _00_0_0 00_000_0000_ 00_ Table shows the results of the RISC processor which performs double precision floating point arithmetic operations for binary. Input (Src) =64 b00 000_00_00_ 000_0000_0000_0000_0000_0000_0000_0000_0000_00 00_0000=53.565d So, Sign=0, Exp=03-7=06, Man=.0* 7 Input (Dst)= 64 b00 000_00_000_ 000_0000_0000 _0000_0000_ 0000_0000_0000_0000_0000_0000=08.565d So, Sign=0, Exp=03-7=06, Man=.0* 7 Table. Results for FPU operations Operation Output in detail Opcode Sign=0 Exp=00000 Man= Float Addition Sign=0Exp=00000 Man= Float Subtraction Sign=0Exp=0000 Man= Float Multiplication Float Division Sign=0Exp= Man= References. Patterson DA, Ditzel DR. The case for the reduced instruction set computer. ACM SIGARCH Computer Architecture News. 980; 8(6): Abraham AE, Sangeetha NR, Monica PR. Canonic signed digit recoding based RISC processor design. Indian Journal of Science and Technology. 05 Aug; 8(8). DOI: / ijst/05/v8i9/ Begum JT, Naidu SH, Vaishnavi N, Sakana G, Prabhakaran N. Design and Implementation of Reconfigurable ALU for Signal Processing Applications. Indian Journal of Science and Technology. 06 Jan; 9(). DOI: /ijst/06/ v9i/ Sravanthi K, Saikumar A. An FPGA based double precision floating point arithmetic unit using verilog. International Journal of Engineering Research and Technology. 03; (0): Gomes SV, Sasipriya P, Bhaaskaran VSK. A low power multiplier using a 4-transistor latch adder. Indian Journal of Science and Technology. 05 Aug; 8(8). DOI: / ijst/05/v8i9/ Sidheeq A. Four stages pipelined 6 bit RISC on xilinx spartan 3AN FPGA. International Journal of Computer Applications. 0; 48(6): Bhosle P, Moorthy HK. FPGA implementation of low power pipelined 3-bit RISC processor. International Journal of Innovative Technology and Exploring Engineering. 0; Kumar JV, Raju BN, Swapna C, Ramanjappa T. Design and implementation of low power pipelined 64-bit RISC processor using FPGA. International Journal of Advanced Research Engineering and Technology. 04; Ravindra J, Anuradha T. Design of low power RISC processor by applying clock gating technique, International Journal of Engineering Research and Applications. 0; (3): Kumar JV, Raju BN, Babu MV, Ramanjappa T. CPLD based design and implementation of low power pipelined 64-Bit RISC processor. International Journal of Emerging Technology and Advanced Engineering. 05; 5(): Kalia K, Bishwajeet P, Teerath D, Hussaian DMA. SSTL based low power thermal efficient WLAN specific 3 bit ALU design on 8 nm FPGA. Indian Journal of Science and Technology. 06 Mar; 9(0). DOI: /ijst/06/ v9i0/ Indian Journal of Science and Technology 5

FPGA Based Implementation of Pipelined 32-bit RISC Processor with Floating Point Unit

RESEARCH ARTICLE OPEN ACCESS FPGA Based Implementation of Pipelined 32-bit RISC Processor with Floating Point Unit Jinde Vijay Kumar 1, Chintakunta Swapna 2, Boya Nagaraju 3, Thogata Ramanjappa 4 1,2Research