Improving Processor Efficiency Through Enhanced Instruction Fetch

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1 Improving Processor Efficiency Through Enhanced Instruction Fetch Stephen Hines Dissertation Advisors: David Whalley and Gary Tyson Department of Computer Science Florida State University March 20, 2008

2 Efficient Processing Mobile computing is everywhere (cell phones, GPS, MP3 players,... ) Balancing device constraints Application performance Power/Energy battery life Code size memory limitations Optimizations often help one area at the expense of another area

3 Fetching Instructions Memory Instructions Processor Instructions need to be fetched from the memory hierarchy before they can be executed Majority of instructions fetched are fairly redundant Repetitive tasks (loops) Programming practices (functions)

4 Exploiting Fetch Behavior The Architect s Toolbox Caching keep recently accessed instructions and data in a faster and smaller memory Speculation guess and fix if wrong My research at FSU Instruction Register File Cache frequent instruction encodings Tagless Hit Instruction Cache Make guarantees instead of speculating

5 Instruction Register File (IRF) Hardware/software approach for lightweight instruction compression/decompression Provides storage (cache) of frequently occurring instructions Instruction packing condenses several instruction register references into a single memory instruction Decreased code size (memory) by 28.83% Reduced overall energy consumption by 15.82% Improved performance by 1.08%

6 Tagless Hit Instruction Cache (TH-IC) Make guarantees about instruction fetch by keeping better track of prior fetch behavior Streamlines the common cases (sequential and branching) Avoids extra performance penalties (6.05%) due to misspeculation by providing a bypass to the L1 instruction cache Reduces overall energy consumption by 27.77% LIFE (Lookahead Instruction Fetch Engine) Extends TH-IC concept to other fetch components Total energy reduced by 34.84%

7 Conclusions Research Achievements Papers at top venues (ISCA 2005, Micro 2005 & 2007,... ) 2 U.S. Patents (IRF + TH-IC) pending NSF Grant (IRF) and 2 GAP proposals funded Working with ARM and Sun, who may incorporate these features into their microprocessors Instruction fetch is an integral part of microprocessor design that can be enhanced through recognition and exploitation of common behaviors What does all of this research mean for you (as a consumer)? Mobile devices have longer battery life without performance degradation and cost less

8 Conclusions Research Achievements Papers at top venues (ISCA 2005, Micro 2005 & 2007,... ) 2 U.S. Patents (IRF + TH-IC) pending NSF Grant (IRF) and 2 GAP proposals funded Working with ARM and Sun, who may incorporate these features into their microprocessors Instruction fetch is an integral part of microprocessor design that can be enhanced through recognition and exploitation of common behaviors What does all of this research mean for you (as a consumer)? Mobile devices have longer battery life without performance degradation and cost less

9 Conclusions Research Achievements Papers at top venues (ISCA 2005, Micro 2005 & 2007,... ) 2 U.S. Patents (IRF + TH-IC) pending NSF Grant (IRF) and 2 GAP proposals funded Working with ARM and Sun, who may incorporate these features into their microprocessors Instruction fetch is an integral part of microprocessor design that can be enhanced through recognition and exploitation of common behaviors What does all of this research mean for you (as a consumer)? Mobile devices have longer battery life without performance degradation and cost less