Xilinx(Ultrascale) Vs. Altera(ARRIA 10) Test Bench

Transcription

1 Xilinx(Ultrascale) Vs. Altera(ARRIA 10) Test Bench By Roy Messinger 1

2 1 GENERAL In the following document I will show a thorough comparison I've conducted between 2 FPGA's of vendor's families; Altera ARRIA 10 & Xilinx UltraScale Kinetis. The comparison put emphasis on frequency, utilization, power & compilation time. I've carried out this comparison in an attempt to find the 'best' vendor suited for my needs. I did not give any 'discounts' to this or that vendor. All the tests I've conducted were purely identical in term of exactly the same code and software preferences. See important notes at last page for further info. 2 WHAT I'VE CHECKED WAS: Frequency. Utilization. Thermal power. Compilation time. 3 FPGA COMPONENTS I ve chosen these FPGA s to compare two similar components, in term of RAM, size, and various other characteristics. Altera Xilinx Component GX480, (10AX048K1F35E1HG) KU035 (XCKU035-1FFVA1156C) System Logic [k] RAM [Mb] PCI-Gen 3 Transcv I/O *8 lanes *8 lanes

3 4 TEST BENCH METHODOLOGY How did I carry out the comparison? For the comparison I have used a VHDL component of a state machine (about 20 states). This FSM implements some heavy logic and runs at 400MHz. I've designed 2 small projects of only this component, both in Altera (Quartus) & Xilinx (Vivado). After each successful compilation, I've checked the timing analysis and replicated the component to push the FPGA capabilities to the edge (space, frequency). I've used virtual pins on all comps so no need to connect the comp ports to the FPGA pins (no connection to IO buffers). I did not alter anything in each of the softwares. I've left the default values of implementation/synthesis setting as they were. Virtual pins Comp. Compile in Vivado & Quartus Passes timing req.? No Compare to second vendor. FPGA Yes Replicate Replicate component 3

4 5 TEST BENCH HARDWARE Compilation computers (both with Windows 7 OS): o Altera: Quartus version (Xeon), 32GB RAM. o Xilinx: Vivado version GB RAM. Component chosen were close to the same spec (to what I need): o Altera: 10AX048K1F35E1HG; GX480, highest speed grade. o Xilinx: XCKU035-1FFVA1156C; KU035, highest slowest speed grade (see notes at last page). o Both comps are the same package dimension (35mm*35mm). 4

5 6 TEST RESULTS I've ran 3 sets of tests. I've defined them as Test A, Test B, Test C. Test A, 400MHz: Each input is connected to all instantiations, as shown. Internal Outputs, obviously, are separated: Test B, 500MHz: Each input is connected to all instantiations, as shown. Outputs, obviously, are separated: Test C, 400MHz: Each input is connected to each instantiation, as shown. Outputs, obviously, are separated:... 2 Clocks are created for the design in SDC (Quartus) & XDC (Vivado); 100MHZ & 400MHz/500MHz This is NOT a real design, but one that can compare the performances between both vendors as it uses a real component and simulates HW FPGA development phases. The code is the same. Test A & Test B are closer to a real world implementation in my point of view, as it defines relations between different instantiations inside the FPGA. Test B is intended to push the FPGA to the edge, in term of frequency, as both vendors do not reach this frequency but are supposed to do their best effort. I've also implemented Test C to ease the vendors Synthesis, Optimizations & Place & Route phases and see what happens then, when there's no relation between different instantiations. The frequency comparison is between the WNS in Vivado (Worst Negative Slack, it's the worse of the worst) and max frequency result in Quartus, which is based on the setup timing in 100c of the timing report (it is the worse of the worst). Both vendor tools have the default preferences (no 'best efforts', etc.). 5

6 Test A (at 400MHz): 6

7 These are the results for 400MHz: Desired freq. Replicated Components Max. Frequency [MHz] Altera Xilinx ARRIA 10 ULTRA- SCALE General Notes & conclusions for Test A: a. The same VHDL component was used with exact same parameters The code is the same. b. Compilation times of Vivado (Xilinx) were 20% faster than Quartus. c. Frequency column values above 400MHz shows the maximum frequency achieved, even though not required. d. Ultrascale(Xilinx) slope is much more stable and linear than ARRIA 10(Altera), and keeps steady slope above the 400MHz target frequency until it cannot hold on. In continuous to section C., I've now compared both projects in 500MHz, where even though both vendors cannot reach such high frequency, they will tend to do their best effort to reach the highest frequency they can. 7

8 Test B (at 500MHz): 8

9 These are the results for 500MHz: Desired freq. Replicated components Xilinx Achieved frequency [MHz] Altera Achieved frequency [MHz] Xilinx Utiization [%] Altera Utilization [%] Xilinx Utilization [LUT] Altera Utilization [ALM] Xilinx Normalized utilization Altera Normalizaed Utilization % Xilinx/Altera usage ,056 38,519 87, , ,825 40,712 92, , ,586 42,715 97, , ,373 44, , , ,158 46, , , ,951 48, , , ,708 51, , , ,506 53, , , ,288 55, , , ,087 57, , , ,803 59, , , ,616 62, , , ,418 64, , , ,152 66, , , General Notes & conclusions for Test B: a. Both vendors could not reach 500MHz, nevertheless, Ultrascale managed to be way over ARRIA 10 in terms of frequency, space and compilation time. b. Regarding logic elements usage, there's a fix value of 86% usage ratio between Xilinx logic usage and Altera logic usage (Xilinx usage is lower than Altera). I've used Xilinx formulas to compare CLB(LUT)'s to ALM's. c. ARRIA 10(Altera) vs. Ultrascale (Xilinx) usage logic ratio is kept fixed all along, showing both Altera and Xilinx replication algorithm does not change, as the usage of logic elements is raising linear when replications increase which is a good thing when comparing apples to apples'. 9

10 Test C (at 400MHz): 10

11 Desired freq. Replicated components Xilinx Achieved frequency [MHz] Altera Achieved frequency [MHz] Xilinx Compilation time Altera compilation time Xilinx Utiization [%] Altera Utilization [%] Xilinx Utilization [LUT] Altera Utilization [ALM] Xilinx Normalized utilization Altera Normalizaed Utilization Xilinx/Altera utilization ratio [%] Power Dissipation Xilinx [W] Power Dissipation Altera [W] :42 15: :48 18: :46 20: :15 21: :58 20: :00 25: :25 28: :32 28: :24 31: :06 32: :47 33: :39 36: :52 37:00 Though pwr dissipation not 'real' because virtual pins are used, still, the comparison between vendors is 'legal' as we can compare between them :00 40: :00 38: :00 39: :20 41: :00 43: :00 45: :00 45: :00 50: :10 52: :00 54: ,448 85, , , :00 56: :00 57: :14 58: ,761 93, , , :30 58: :00 01:01: :37 01:05: :21 59: :00 01:07: :30 01:10: , , , , :03 01:02: :00 01:11: , , , , :55 01:01: :52 01:13: :03:00 01:12: , , , , :04:00 01:19: :05:01 01:22: :09:00 01:23: :06:00 01:29:

12 General Notes & conclusions for Test C: a. In this test, though less realistic in my point of view, both vendors can hold more replications till they fail timing requirements. Nevertheless, ARRIA 10 (Altera) keeps failing at much earlier points than Ultrascale (Xilinx). b. Xilinx Compilation times are about 20% faster than Altera. c. Regarding logic elements usage, there's a fix value of 65% usage ratio between Xilinx logic usage and Altera logic usage (Xilinx usage is lower than Altera). I've used Xilinx formulas to compare LUT's to ALM's. d. In this test I've also compared Thermal Power: Ultrascale consumes about 50% less power than ARRIA 10 (meaning less overall heat and power supply current needed). 12

13 7 TEST RESULTS SUMMARY So, overall: A. When comparing Altera ARRIA 10 GX480, F35, to Xilinx UltraScale KU035, A1156: Compilation time (Xilinx 20% less). Frequency (Xilinx were much more stable and higher freq.) Thermal power (Xilinx almost 50% less power). Utilization (Xilinx to Altera ratio 86%). B. Even when I compared Altera s GX320 to Xilinx s KU035 (Altera smaller comp to 'same' Xilinx comp), the Xilinx s KU035 had better results, in all these characteristics. For example, when compiling Altera s GX320, F35 (same package as Altera s GX480) which should be 'equal' to Xilinx s KU035, for 44 replications: Quartus utilization for GX320 for 44 replications, Test C: Logic utilization (in ALMs) 139,107 / 119,900 ( 116 % ) And compilation failed. Not enough place in device. Xilinx utilization for KU035 for 44 replications, Test C: 60%. C. When compared ARRIA 10 GX270 to Xilinx s KU035, I had similar results in all characteristics (did not check all replications). Notes: 2 very important keynotes I've discovered after conducting this comparison (which should tip the scale in favor of Intel/Altera, and nevertheless, Xilinx results are much better): Xilinx FPGA chosen was smaller than Altera. This means Xilinx P&R algorithm must work harder to reach the desired frequency (since less space is available). Nevertheless, Xilinx results are much better. Xilinx FPGA speed is the slowest, compared to Altera (which is the fastest). This means Altera results should be better. Nevertheless, it is much worse. 13