Image Processing using Dynamic Partial Reconfiguration on Zynq Shruti Karbhari December 10, 2018

Transcription

1 Image Processing using Dynamic Partial Reconfiguration on Zynq 7020 Shruti Karbhari December 10, 2018

2 Motivation Image processing algorithms can be resource intensive Depending on the algorithm, they could require multiple DSP elements and block RAMs. DPR provides the ability to selectively swap algorithms in and out of the PL Done using the PCAP interface Required device size can be reduced in this case 2

3 System Overview PL PS SD card DDR AXI-Full Slave Interface AXI WDATA ififo 512*32 iaempty 24-bit RGB data RM1 RGB2gray Y=0.21*R *G *B M U X RP 8-bit grayscale data Output Data Latch 32-bit data ofifo 512*32 AXI-Full Slave Interface AXI RDATA DDR SD card PS AXI Interface FSM PR reset rst irden Input Sync Generator FSM FV,LV,DV RM2 Edge Detection FV,LV,DV out latch_data_op owren oafull Output FSM SW0 (F22) IMG_PROC _EN 3

4 Reconfigurable Partition (RP) Overview 1 Reconfigurable Partition 2 Reconfigurable Modules RM1: RGB2gray Y=0.21*R *G *B RM2: Edge Detection 2-D convolution using the kernel The result from 3 channels is averaged to get the final 8-bit value MUX is used to select between bypassed image or processed image for debugging purpose 4

5 RM2: Edge Detection 2-D convolution using the kernel Border pixels don t have enough context Output is set to zero Negative values after convolution are converted to their absolute values The result from 3 channels is averaged to get the final 8-bit value If the result of the average is more than 255, it is clipped to Line Buffers to provide data for context 5

6 Image Input Process Input image is 256x bit RGB PS sends one line ( bit words) to PL 24-bit RGB data is padded with zeros The almost empty flag of the input FIFO deasserts Almost empty threshold is 256 One line of data is sent to the RM Process continues until all the lines are written 6

7 PL: Input Sync Gen FSM IDLE iempty=1 SOF iaempty=0 IN_LINE irden=1 fv,lv,dv=1 pcnt++ pcnt<256 pcnt<270 iaempty=0 BLANK_HOR irden=0 lv,dv=0 pcnt++ lcnt<256 WAIT_SOL lcnt++ pcnt=0 lcnt=256 START_BLAN K_VER fv=0 lv=dv=1 pcnt=0 lcnt<270 lcnt=270 IN_LINE_BLA NK_VER dv=1 pcnt++ BLANK_HOR_ VER pcnt++ lv=1 pcnt<256 7 pcnt<270

8 PL: Image Output Process Output image is 256x256 8-bit grayscale 4 8-bit pixels are latched and combined to make a 32-bit word i.e. one line = 256/4 = 64 words The almost full flag of the output FIFO deasserts Almost full threshold is 64 One line of data is sent from the RM 8

9 PL: Image Output FSM IDLE oafull=0 & fv=lv=dv=1 LATCH_DATA_1 latch_op=001 pcnt++ fv=lv=dv=1 LATCH_DATA_2 latch_op=010 pcnt++ fv=lv=dv=1 LATCH_DATA_3 latch_op=100 pcnt++ owren=1 fv=lv=dv=1 pcnt<256 CHK_PCNT latch_op=000 owren=0 9

10 Dynamic Partial Reconfiguration Process Start with RGB2Gray bitfile Transfer RGB2Gray bitfile Send image Reset the RP Run image processing Send image Retrieve image Run image processing Transfer Edge Detection bitfile Retrieve image Reset the RP Send image Run image processing Retrieve image 10

11 Results:RGB2Gray Matlab reference HW output 11

12 Results: Edge detection Matlab reference HW output 12

13 Conclusion DPR Challenges Floorplanning Selected Pblock should accommodate elements required by all RMs in the least amount of space Interface definition The interface should be common between the two RMs Proper reset procedure should be followed to ensure the RP starts from an idle state Ability to effectively debug in hardware 13

14 Thank You 14