Reliability Measurement of FPGA Implementations on Software-Defined Radio Platforms

Transcription

1 Reliability Measurement of FPGA Implementations on Software-Defined Radio Platforms Presented by Dr. Armando Astarloa APERT June 2013

2 Index Introduction and Motivation 1 Introduction and Motivation 2 SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures 3

3 1 Introduction and Motivation 2 SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures 3

4 Parameters (λ): Device s failure rate. Failure In Time (FIT) rate: Number of failures that can be expected in 10 9 device-hours of operation. Figure: The Bathtub curve [1]. Figure: Evolution of the Bathtub curve.

5 Parameters Reliability (R(t)): The probability of an electronic system to perform its required functions under stated conditions for a specified period of time. R(t 1 ) is the probability of a system will not fail in time t 1. R(t) = e λt (1) Mean Time Between Failures (MTBF): Average time a system runs between failure. MTBF = 0 e λt dt = 1 λ (2)

6 Temporal errors in electronic devices Single Event Effects (SEEs): 1 Heavy ion strikes the silicon 2 It loses its energy via the production of free electron hole pairs 3 A dense ionized track in the local region is generated 4 A bit-flip can be induced (SEU, SET, SEFI, MBU, SEL -permanent-) Figure: An ion passing through a transistor

7 Fault tolerance techniques in electronic devices Redundancy: Physical redundancy: Plain design, Tripe Modular Redundancy with simple voter, Partitioned Tripe Modular Redundancy with multiple simple voters, XTMR. Temporal redundancy: Same processing (t) and further comparison. Figure: Tripe Modular Redundancy with simple voter.

8 Standard for Functional Safety and Certifications Electronic products certification for critical applications Analysis and development methods Safety integrity levels: SIL1-SIL4 (IEC 61508) Two modes of operation: High demand rate and Low demand rate

9 Safety integrity levels Table: IEC Safety integrity Level for high demand rate systems (dangerousfailures/hr) Safety integrity Level SIL4 SIL3 SIL2 SIL1 λ required between 10 8 and 10 9 between 10 7 and 10 8 between 10 6 and 10 7 between 10 5 and 10 6

10 The electronic design is living a revolution Current status: New silicon technologies allow the integration of whole digital systems in a single chip The design of Application Specific Integrated Circuits is more and more expensive, complex and risky

11 Answer: Reconfigurable logic (FPGAs) What is a FPGA?: It is similar to a un-formatted chip It can be load with a custom circuit designed using specific EDA tools Modern FPGAs offer similar features to ASICs

12 FPGAs trade-off Introduction and Motivation Challenges: Success keys: Affordable engineering Low risk: Reconfigurable Low product time-to-market Flexible electronic boards (they can be reused for different products) Susceptible to SEE (SEUs) Programmability (Safety standards) Example: Virtex-5 nominal 131 FIT/Mb configuration cells [2] XC5VLX50T 11,37 Mb of configuration cells > 1489 FIT nominal or an MTBF of 77 years

13 NASA SpaceCube (source [3]) Figure: SPACE cube 1.0 CPU. Figure: STS-125 launch. Figure: California wildfire scene

14 Temporal errors in FPGAs Figure: FPGA architecture. Figure: SEU effect in FPGAs.

15 COMB X LOGIC X X X A B COMB LOGIC OK OK OK MAJORITY VOTER X COMB LOGIC CLK Figure: Tripe Modular Redundancy with simple voter in a FPGA. [4]

16 MAJORITY VOTER MAJORITY VOTER MAJORITY VOTER MINORITY VOTER MINORITY VOTER MINORITY VOTER Introduction and Motivation XTMR architecture - XTMR triplicates: All inputs including clocks and throughput (combinational) logic. Feedback logic and inserting majority voters on feedback paths. All outputs, using minority voters to detect and disable incorrect output paths. COMB LUT LOGIC TR0 A COMB LUT LOGIC B TR1 CLK COMB LUT LOGIC TR2 Figure: XTMR architecture. X

17 XTMR design flow: ISE Project (.NGC) (.NGC) Translate (NGDBuild) Generar Netlis XTMR (.EDF) Translate (NGDBuild) Ma p Ma p BitGe n BitGe n.bin.bin P a s o 1 Proyecto Pre -XTMR P a s o 2 Proyecto TMR Tool P a s o 3 Proyecto Post -XTMR Figure: XTMR design flow.

18 Scrubbing: Memory Original Frame Data Erroneous Frame Data Comparator FPGA Modifier Corrected Frame Data Figure: Scrubbing concept.

19 Internal Scrubbing combined with Error Correcting Code (ECC): Configuration Memory FPGA Primitives ICAP DMA PicoBlaze BRAM Frame ECC ICAP PicoBlaze Processor Control Logic DMA BRAM Figure: SEU controller macro in Virtex-5 [5].

20 Block RAMs Scrubbing (Internal RAM memory): CEN_BSCNT_TMR[0 1 2] Data_Out[0 1 2] CEN_BSCNTR_TMR[0 1 2] EN[0 1 2] Address_CNTR VD Data_Voter0 ERROR Voted_Data0 Din_B Data_OutB0 AB BRAM_Block0 Web ADDRA_[0 1 2] + WEA[0 1 2] CNT_TR[0 1 2] Address_B[0 1 2] Error_indication[0 1 2] Voted_Data1 VD Data_Voter1 ERROR Din_B Data_OutB1 AB BRAM_Block1 Web COMPARATOR Voted_Data2 ENB[0 1 2] WEB[0 1 2] BRAM ENB for Address Compare VD Data_Voter2 ERROR Din_B Data_OutB2 AB BRAM_Block2 Web Figure: BlockRAM scrubber macro block diagram [6].

21 Partial Reconfiguration for Fault Tolerance Partial reconfiguration is supported by Xilinx Technological challenges overcome (Virtex-4): Internal reconfiguration ports (ICAP) No frame restriction (16-CLB range) No SRL16 and LUT RAMs limitations RPD Design flow enhanced

22 SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures 1 Introduction and Motivation 2 SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures 3

23 SEU Test Set-up Test Flow Introduction and Motivation SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures Evaluation Board (EB) FPGA RS232 TMR_CLK 3 3 TMR_UART COM1 COM2 USB FPGA RS232 Board Under Test (BUT) JTAG

24 Data Key Start Out Rdy Data Key Start Out Rdy Data Key Start Out Rdy Data Key Start Out Rdy Introduction and Motivation Analysis Results for Cipher Blocks Test Flow SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures Analyzed SEU Resilience of the following VHDL Cipher Blocks [7]: (1) (2) Inject SEU or MBU into original bitstream program device with altered bitstream DES [8] AES [9] Twofish [10] (3) send input read output of the (4) cipher chain verify correct operation and (5) log current testrun next input UART_in RS232 receive RX Register Blockcipher core 0 Blockcipher core 1 Blockcipher core 2 Blockcipher core n Mux RS232 transmit UART_out

25 Analysis Results for Cipher Blocks Analysis Results SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures Injection Estimation Mean Time Between Failure in years DES AES TwoFish

26 SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures Analysis Results for on-chip bus Architectures Redundant Architectures Compared Inject SEU or MBU into random bitstream position next testrun program device using modified configuration stream run application on FPGA and read device output check output against expected and log the test run (a) Test Flow (b) Wishbone shared interconnection [11]

27 Instance 2 Instance 2 Instance 2 Instance 2 Instance 2 Instance 2 Introduction and Motivation SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures Analysis Results for on-chip bus Architectures Redundant Architectures Compared UART Voter to PC UART Voter to PC CLK0 CLK1 CLK2 Master 0 Master 1 Master n TMR TMR TMR master TMR 0 master TMR 1 master TMR n master 0 master 1 master n Master 0 Master 1 Master n M0 Voter M1 Voter Mn Voter CLK0 CLK1 CLK2 CLK Shared WishBone Inter- connection Shared WishBone Inter- connection Shared WishBone Inter-... connection Arbiter Arbiter Arbiter Shared WishBone Inter-... connection Arbiter Arbiter Arbiter TMR TMR TMR slave TMR 0 slave TMR 1 slave TMR m slave 0 slave 1 slave m Slave 0 Slave 1 Slave m S0 Voter S1 Voter Sm Voter RST RST0 RST1 RST2 RST2 RST1 RST0 Slave 0 Slave 1 Slave m (c) Coarse-grained TMR (d) Medium-grained TMR

28 SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures Analysis Results for on-chip bus Architectures Analysis Results Table: Test Results for External and Internal voting Error type Testruns Coarse-grained Errors Percent Medium-grained Errors Percent SEU bit-MBU bit-MBU bit-MBU bit-MBU bit-MBU

29 SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures Analysis Results for on-chip bus Architectures Analysis Results Table: Categories of test results Cat. A B C D E Description All TMR layer counters are zero One TMR layer counter differs from zero Two or three of the TMR layer counters differ from zero Two or three of the TMR layer counters differ from zero Two or three of the TMR layer counters are zero System behavior Correct Erroneous

30 SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures Analysis Results for on-chip bus Architectures Analysis Results 100% 9,7% 90% 15,9% 18,5% 24,7% 2,7% 4,4% 80% 29,4% 34,7% 70% 60% Cat.D 50% 40% 90,3% 83,7% 80,9% Cat.C Cat.B Cat.A 73,5% 67,2% 30% 59,8% 20% 10% 0% SEU 2bit-MBU* 2bit-MBU 3bit-MBU 4bit-MBU 5bit-MBU

31 1 Introduction and Motivation 2 SEU Test Set-up Analysis Results for Cipher Blocks Analysis Results for on-chip bus Architectures 3

32 Partial Reconfiguration and TMR on FPGA based Rugged Systems SafeVPX has 3U Eurocard size and it can run in stand-alone mode or it can be plugged in a 3U VPX (VITA 46, air-cooled) back-plane. In this last case, SafeVPX supports 3 fat-pipes. Each fat-pipe is composed of four bidirectional Multi-Gigabit-Transceiver (MGT) links. Each fat-pipe channel allows the implementation of PCIe x4, Aurora or other protocol among high-speed communication standards.

33 Key features Features Virtex-5 FPGA (5VFX100-TFF1136) industrial range Hard PowerPC processor FPGA embedded CRC protected DDR2 memory (5 Gb) 2 isolated CAN communication channels 1 isolated serial communications link 3 isolated sigma-delta ADCs 1 SFP connector (Gigabit Ethernet or Fibre Optics) Ready for stand-alone or VPX racked operation 3U Eurocard factor form (3U VPX VITA 46) FMC connector (only available for stand-alone (operation mode) Multiple options for full and partial bitstreams storage Extended temperature range FPGA ready for Xilinx X-TMR implementation: Triplicated clock inputs Triplicated CAN communication lines Triplicated serial communication lines Triplicated General Purpose I/Os

34 Introduction and Motivation Combination with SDR boards RuggedSDR Boards(VPX or stand-alone) Last generation Software-DefinedRadio boards for air or conduction cooled systems

35 Air-cool or Conduction-Cool SDRlab Chassis 3U VPX Laboratory Equipment with Power Supply and easily removable cover LightVPX Chassis 3U Conduction-cooled chassis and clamshells

36 Reliability in electronics systems is a challenge with nowadays levels of integration and complexity Modern FPGAs and SoPCs are the key circuits in state-of-the-art boards Error mitigation and Fault Tolerance traditional techniques are applicable with FPGAs Experimental analysis techniques combined with the use of standards defined for rugged systems can ensure high levels of reliability on SDR Platforms

37 Research Projects: This work has been partially supported by the Ministerio de Ciencia e Innovación of Spain within the project TEC C This work has been carried out inside de Research and Education Unit UFI11/16 of the UPV/EHU and supported by the Department of Education, Universities and Research of the Basque Government within the fund for research groups of the Basque university system IT

38 Thank you for your attention!

39 C. Constantinescu, Trends and challenges in VLSI circuit reliability, IEEE Micro, vol. 23, no. 4, pp , Xilinx Corp., Device reliability report, fourth quarter 2010, Xilinx Documentation, Feb D. Petrick, T. Flatley, A. Geist, D. Espinosa, G. Crum, M. Lin, J. Hosler, M. Buenfil, and K. Blank, SpaceCube: Current Missions and Ongoing Platform Advancements, in Military and Aerospace Programmable Logic Devices (MAPLD), A. Morillo, A. Astarloa, A. Zuloaga, U. Bidarte, and J. Lázaro, Técnicas de diseño seguro con FPGAs, in XVII Seminario Anual de Automática, Electrónica Industrial e Instrumentación (SAAEI10), vol. ISBN , K. Chapman and L. Jones, SEU strategies for Virtex-5 devices, XAPP864, 2009, Xilinx Inc. G. Miller, C. Carmichael, and G. Swift, Single-Event Upset Migration for Xilinx FPGA Block Memories, Xilinx Application Notes, notes/xapp962.pdf, Mar U. Kretzschmar, A. Astarloa, and J. Lázaro, Seu resilience of des, aes and twofish in sram-based fpga, in Reconfigurable Computing: Architectures, Tools and Applications. Springer, 2013, pp Tetraedre Sarl, Auvernier, TCDG - DES cryptographic module, sep H.Satyanarayana, AES128 - Project: aes crypto core, OPENCORES dec Opencores.org, Twofish - Project: Twofish Core, OPENCORES feb

40 U. Kretzschmar, A. Astarloa, J. Lazaro, M. Garay, and J. Del Ser, Robustness of different tmr granularities in shared wishbone architectures on sram fpga, in Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on, 2012, pp. 1 6.