Chapter 1. Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Dept. of Electrical Engineering. Jhongli, Taiwan

Transcription

1 Chapter 1 Introduction to Memorie Advanced Reliable Sytem (ARES) Lab. Dept. of Electrical Engineering it Jhongli, Taiwan

2 Outline Importance of Embedded Memorie Overview of Memory Structure 2

3 Embedded Memory The Key to SOC Embedded memory i becoming more central to integrated circuit deign Hitorically, IC were dominated by the logic function, with memory being external Today, an SOC contain many memory block of different ize, hape and functionality Typically, embedded memorie repreent about 30%~50% SOC area The Semiconductor Indutry Aociation (SIA) predict that 90% of the SOC urface will be memory in

4 Embedded Memory The Key to SOC SOC memory continue to increae Memory Area Reued Logic Area New Logic Area 20% 16% 52% 71% 83% 90% 94% 64% 16% 13% 32% 9% 6% 16% 4% 8% 4% 2% * 08* 11* 14* *Foreat Source: SIA, ITRS,

5 Embedded Memory Advantage Area Embedding multiple memorie on a ingle SOC reduce the amount of ilicon ued Performance Embedding fater, wider memorie and moving them cloer to proceor can increae ytem performance ubtantially Power Embedded memorie eliminate the need to drive off-chip capacitance between the tand-alone memorie and other ytem chip Deign reue By reuing embedded memorie, ytem deigner can ignificantly reduce develop time and cot 5

6 Embedded Memory Quality During manufacture Yield Exponential yield model AD Y = e, where A and D denote the area and defect denity, repectively After manufacture Reliability During ue Soft error rate National Central Univerity 6

7 Quality During Manufacture Iue of embedded memory A the denity of tranitor i increaed, the D i increaed compared to logic About 2X logic for high denity 6-T SRAM Solution Redundancy d & laer repair uing ATE Error correction code (ECC) Redundancy & repair Achieve yield parity with logic, or better About 3% area overhead Recommended over 1Mb National Central Univerity 7

8 Quality During Manufacture Correct <5 defect per Mb Laer repair manufacturing flow ECC Detect/repair defect in individual word 25-30% area overhead Ex: 6 extra bit for ingle bit correction in 32 bit word Latency penalty At leat one clock cycle latency penalty National Central Univerity 8

9 Quality-Inurance Strategie for Memorie Memory Teter Laer Repair Memory Teter.Large Capture Memory.Redundancy analyi.swap the defective cell.tet the repaired memorie Conventional tet and repair approache 1. Long teting time 2. Expenive memory teter and logic teter are needed Logic Teter.Tet the remaining non-memory component.tet Built-In Self-Tet (BIST) BIST & BISR approache 1. Short teting time 2. Only cheap logic teter i needed.diagnotic.redundancy allocation Built-In Self-Diagnoi (BISD) Built-In Redundancy Analyzer (BIRA).Swap the defective cell Redundancy Reconfiguration 9

10 Introduction to Memorie Overview of emiconductor memory type Semiconductor Memorie Read/Write Memory or Random Acce Memory (RAM) Read Only Memory (ROM) Random Acce Memory (RAM) Static RAM (SRAM) Dynamic RAM (DRAM) Regiter File Non-Random Acce Memory (RAM) Mak (Fue) ROM Programmable ROM (PROM) Eraable PROM (EPROM) FIFO/LIFO Electrically EPROM (EEPROM) Shift Regiter Flah Memory Content Addreable Ferroelectric RAM (FRAM) Memory (CAM) Magnetic RAM (MRAM) 10

11 Memory Element Memory Architecture Volatile memorie may be divided into the following categorie Random acce memory Serial acce memory Content addreable memory Memory architecture 2 m+k bit row decoder row decoder row decoderd row decoder 2 n-k word k n-bit addre column decoder m-bit data I/O column mux, ene amp, write buffer 11

12 1-D Memory Architecture S 0 Word 0 S 0 Word 0 S 1 Word 1 S 1 Word 1 S 2 S 3 Word 2 Word 1 S 2 A 0 A 1 er Decod S 3 Word 2 A k-1 S n-2 Word n-2 Storage element S n-2 Word n-2 S n-1 Word n-1 S n-1 Word n-1 m-bit Input/Output m-bit Input/Output n elect ignal: S 0 -S n-1 n elect ignal are reduced to k addre ignal: A 0-A k-1 12

13 2-D Memory Architecture S 0 Word 0 Word i-1 S 1 A 0 A 1 A k-1 Row De ecoder S n-1 Word ni-1 A 0 A j-1 Column Decoder Sene Amplifier Read/Write Circuit m-bit Input/Output 13

14 3-D Memory Architecture ock Blo Column Row Input/Output 14

15 Conceptual 2-D Memory Organization Addre Ro ow Decod der Memory Cell Column decoder Data I/O 15

16 Memory Element RAM Generic RAM circuit Bit line conditioning Clock RAM Cell n-1:k k-1:0 Sene Amp, Column Mux, Write Buffer Write Clock Addre write data read data 16

17 Memory Element RAM Cell 6-T SRAM cell word line 4-T SRAM cell bit - bit word line bit - bit 17

18 Memory Element RAM Cell 1-T DRAM cell word line word line bit bit Layout of 1-T DRAM (right) Vdd word line bit 18

19 Memory Element DRAM Retention Time Write and hold operation in a DRAM cell WL=1 WL=0 Input Vdd + - on C + - V off C + - V Write Operation Hold V Q = max V max = C = V DD V tn ( V V ) DD tn 19

20 Memory Element DRAM Retention Time Charge leakage in a DRAM Cell WL=0 V max V (t) I L off + C - V (t) V 1 Minimum logic 1 voltage t h t I I I t L L L h dq = ( ) dt dv = C ( ) dt Δ V C ( ) Δ t C = Δ t ( ) Δ V I L 20

21 Memory Element DRAM Refreh Operation A an example, if IL=1nA, C=50fF, and the difference of V i 1V, the hold time i t h = 1 = 0.5μ Memory unit mut be able to hold data o long a the power i applied. To overcome the charge leakage problem, DRAM array employ a refreh operation where the data i periodically read from every cell, amplified, and rewritten. The refreh cycle mut be performed on every cell in the array with a minimum i refreh frequency of about f refreh 1 2t h 21

22 Memory Element DRAM Read Operation WL=1 on I L + C bit + - V bit V f C - V V f Q Q = = C C V V f C + C bit V f = ( ) C + C bit Thi how that V f <V for a tore logic 1. In practice, V f i uually reduced to a few tenth of a volt, o that the deign of the ene amplifier become a critical factor V V f 22

23 Memory Element RAM Read Operation precharge precharge bit, -bit word line word data -bit bit data 23

24 Memory Element RAM Write Operation word N 5 N 6 write data write N 3 N 4 word -bit bit bit, -bit write N 1 N 2 write data cell, -cell 24

25 Memory Element Row Decoder word<3> word<0> word<2> word<1> word<1> word<2> word<0> word<3> a<1> a<0> a<1> a<0> 25

26 Memory Element Row Decoder Predecode circuit word<7> word<6> word<5> word<4> word<3> word<2> word<1> word<0> a2 a1 a0 26

27 Memory Element Row Decoder Actual implementation a0 a4 a3 a2 a1 word -a0 clk Peudo-nMOS example a0 word od a1 a2 en 27

28 Memory Element Column Decoder bit<7> bit<6> bit<5> bit<4> bit<3> bit<2> bit<1> bit<0> -bit<7> -bit<6> -bit<5> -bit<4> -bit<3> -bit<2> -bit<1> -bit<0> elected-data to ene amp and write ckt -elected-data a0 -a0 a1 -a1 a2 -a2 28

29 Memory Element Multi-Ported RAM write read0 read1 -rbit1 -rbit0 -rwr_data rwr_data rbit0 rbit1 write read0 read1 -rbit1 -rwr_data rwr_data rbit0 29

30 Memory Element ROM A 4x 4-bit NOR-baed ROM array R1 R2 R1 R2 R3 R4 C1 C2 C3 C R R4 C1 C2 C3 C4 30

31 Memory Element ROM A 4x 4-bit NAND-baed ROM array C1 C2 C3 C4 R1 R2 R3 R4 R1 R2 R3 R4 C1 C2 C3 C

32 Memory Element ROM Typical ROM architecture 2 N word line NOR Row Decoder NOR ROM Array 1 23 N Addre bit 2 M column 32