Spring 2012 EE457 Instructor: Gandhi Puvvada

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1 Spring 2012 EE457 Intructor: Gandhi Puvvada Quiz (~ 10%) Date: 2/17/2012, Friday in SLH200 Calculator and Cadence Verilog Guide are allowed; Time: 10:00AM-12:45PM Cloed-book/Cloed-note Exam Total point: 284 Name: Student ID: Do NOT write any ID (tudent ID, SSN,..) Perfect core: 270 / ( = 56 point) 30 min. State Diagram and RTL deign: Thi i a imple modification to Lab 1 Part2 Min/Max finder uing one comparion unit. The original incomplete tate diagram i redrawn and given on the next page. Here again the array i a 16x8 array containing 16 unigned 8-bit number. There are two difference. 1. Some of the number are valid and ome are not. So there a valid array V[0:15]. When you read the next M[I], you alo read the next V[I]. If it i invalid V[I] = 0, then you imply dicard it and go to the next number. It i never the cae that all 16 number are invalid. There i at leat one valid number. 2. The ingle comparion unit i hared between thi application and another high-priority application. The high-priority application (running on the ame clock) can take away the comparator from u and tell u that the comparator i buy (CB = 1). Complete the tate diagram on the next page by adding additional tate tranition arrow a needed and carefully uing V[I]and CB (or their compliment) and perhap (I==14) and/or (I==15) and/or (I==16) and their complement a needed to qualify your tate tranition condition and RTL operation Aume that CB i alway zero (CB = 0) (i.e. comparator i never buy) for thi part of the quetion. The total number of clock taken (in the LOAD, CMx and CMn tate) will be the leat : (i) if there i only one data, that i valid True / Fale (ii) if all the valid data are in acending order True / Fale (iii) if all the valid data are in decending order True / Fale How many clock i that leat number of clock? What i the maximum number of clock you could pend in the LOAD, CMx and CMn tate? And what kind of data will caue thi happen? The counter I i cleared (ynchronouly / aynchronouly) (by Reet only / by Reet beide while in INI tate / while in INI tate). The counter I incremented unconditionally in tate() and conditionally in tate(). If "None", write "None". February 17, :27 am EE457 Quiz - Spring / 8 C Copyright 2012 Gandhi Puvvada

3 2 ( = 52 point) 30 min In our ALU_SLT lab, we could figure out if the 4-bit A (A3 A2 A1 A0) i le than the 4-bit B (B3 B2 B1 B0) (treating A and B a igned number), by looking at (V / COUT4) beide the MSB of the 4-bit difference, which wa called SET (= ADD_R[3]) in our lab. In our lab, the ALU lice (= building block) ha the ADD_R ignal (called SET in the book) brought out for all lice, unlike in the book where it wa brought out for the MSB (motignificant block) only. Hence we could form ADD_R[3:0] a the 4-bit reult of the ubtraction A - B provided BNEG i tied to a (0 / 1) and Opr (the 2-bit operation control input going to the 4-to-1 muxe in the building block) i tied to (00 / 01 / 10 / 11 / any one of them or even XX). Thi 4-bit difference could be wrong (treating A and B a igned number), if (V / COUT4) i a (0 / 1). A tudent ha concatenated LESS_0 to ADD_R[3:0] to form the 5-bit number LESS_0 ADD_R[3] ADD_R[2] ADD_R[1] ADD_R[0]. Comment on thi 5-bit number Given two 4-bit number X (X3 X2 X1 X0) and Y (Y3 Y2 Y1 Y0), produce an 8-bit number S (S7 S6 S5 S4 S3 S2 S1 S0) uch that S = 8X - 4Y = 4*(2X - Y) uing the 5-bit adderubtractor given below and a few gate (not a few Full_ADDER). Here all three (X, Y, S) are igned number repreented in 2 complement notation. The 8-bit number S i (alway correct / ometime wrong). If your anwer i "ometime wrong", then produce SOV tanding for igned overflow. Alo, treating X and Y a unigned 4-bit number, produce the 8-bit unigned number US (US7 US6 US5 US4 US3 US2 US1 US0) uch that US = 8X - 4Y = 4*(2X - Y). The 8-bit number US i (alway correct / ometime wrong). If your anwer i "ometime wrong", then produce USOV tanding for unigned overflow. X1 X0 ADD/SUB Carry RawCarry C0 V Larget negative 4*(2X - Y) for igned number i when X = -8 and Y = +7, when 4*(2X - Y) =, and larget poitive value of occur when X = +7 and Y = -8. Both thee (do / don t) fit in the 8-bit S. The range of 8-bit igned number i (-8 to +7 / -32 to +31 / -128 to +127 / none of thee). Larget 4*(2X - Y) for unigned number i when X = 15 and Y = 0, when 4*(2X - Y) = which (doe / doen t) fit in the 8-bit S. There (are ome / aren t any) combination of X, Y, which make 4*(2X - Y) negative which i unrepreentable in unigned S. The range of 8-bit unigned number i (0 to 15 / 0 to 63 / 0 to 255). February 17, :27 am EE457 Quiz - Spring / 8 C Copyright 2012 Gandhi Puvvada

4 3 ( = 44 point) 15 min Thi i imilar to the Fall 2011 quetion. If any tate machine get tuck in DEC tate, then jut ay o and do not fill the value. #3 i ubtantially different from other. ~RESET ~RESET START INI (INITIAL) I <= 15; J <= 15; K <= 15; #1 START INI (INITIAL) I <= 15; J <= 15; K <= 15; #2 DEC START (DECREMENT) (I = J) and (J!= K) K <= J; J <= I if (I > 13) I <= I - 1; END (I = J) and (J!= K)!= END DONE (DONE) Number of clock pent in DEC tate Value of I, J, and K in the DONE tate: I = ; J = ; K = ; DEC START (DECREMENT) (I = J) and (J = K) K <= J; J <= I END (I = J) and (J = K) I <= I - 1; END DONE (DONE) Number of clock pent in DEC tate Value of I, J, and K in the DONE tate: I = ; J = ; K = ; = #3 Here, the DEC tate i decribed in Verilog. Following i the DEC cae branch of the cae tatement in a clocked alway block. The INI and the DONE tate are the ame a before. DEC: begin I <= I - 1; if (I == J) J <= J - 1; if (J == K) K <= K - 1; if ((I == J) && (J == K)) I <= I - 2; if (I == 12) STATE <= DONE; end Number of clock pent in DEC tate Value of I, J, and K in the DONE tate: I = ; J = ; K = ; (A later/ An earlier) aignment in HDL procedural (begin-end) block over-ride an (later / earlier) aignment Complete the two verilog code (for the tate tranition for tate S0) to uit the tate diagram. S0: begin tate <= S1; ele tate <= S2; ele tate <= S3; end 3.3 Complete the ection of tate diagram below a per the code on the right. S6 S5 S7 S8 S1 A February 17, :27 am EE457 Quiz - Spring / 8 C Copyright 2012 Gandhi Puvvada S0 S2 A B A B C A B C S3 X YZ Y X 1 S0: begin tate <= S3; Z tate <= S2; tate <= S1; end S5: begin if ((~X)&(~Y)) tate <= S6; if (Z) tate <= S7; if (X) tate <= S8; end

5 4 ( = 50 point) 25 min. Performance In the ISA of a particular CPU, there are only four type of intruction: A, B, C, and D taking individual CPI of 2, 3, 4, and 5 repectively. Thi CPU run at 1GHz (CP = 1n) Calculate MIPS and tate whether what you calculated hould be called Native MIPS or Relative MIPS. Frequency = Frequency of occurrence in the dynamic trace of execution Category CPI frequency A B C % 30% 20% D 5 10% MIPS = It i (Native / Relative) MIPS It i propoed to improve the D category of intruction o that they take only 4 clock intead of 5 clock, but it require that the clock period i increaed by 2% (intead of the current 1n clock, it would be 1.02n clock). If you have enough data, arrive at performance improvement/ degradation. If you do not have enough data tate what ele you need Another (independent) propoal i to ue a compiler from another vendor. Thi compiler ue 10% more intruction (IC increae to IC*1.1) but avoid uing D type intruction totally a hown below. If you have enough data, arrive at performance improvement/degradation. If you do not have enough data tate what ele you need. Frequency = Frequency of occurrence in the dynamic trace of execution Category CPI frequency A B C % 30% 20% D 5 0% Adding a Floating Point Multiply hardware to improve performance will caue (a) Native MIPS to (go up / go down / remain the ame). (b) Relative MIPS to (go up / go down / remain the ame). (c) MFLOPS to (go up / go down / remain the ame). February 17, :27 am EE457 Quiz - Spring / 8 C Copyright 2012 Gandhi Puvvada

6 5 ( 20 point) 10 min. You know how to deign a 4-bit ALU to upport SLT (for igned number), SLTU for unigned number, and alo to produce 1-bit reult called ZERO (which can be called EQUAL) which i the ame for both igned and unigned number. The key ignal for the 4-bit SLT output i LESS_0. The key ignal for the 4-bit SLTU output i LESS_0U (U for Unigned). Uing two of thee ALU (a hown below), and combining their individual inference of comparing lower nibble and upper nibble, produce LESS_0_8, LESS_0U_8, and ZERO_8 for double preciion 8-bit operation (the _8 indicate reult for 8-bit operation). It (i / in t) poible to produce V_8 and Raw_Carry_8 without altering (any / one / both) of the 4-bit ALU. Mr. Trojan hinted that, to make an 8-bit igned comparator, he would buy one 4-bit igned comparator and another 4-bit unigned comparator (note unigned). Complete the deign below. AL BL AH BH LOWER L = Lower 4-bit ALU HIGHER H = Higher 4-bit ALU LESS_0 LESS_0U ZERO V Raw_Carry LESS_0 LESS_0U ZERO V Raw_Carry A_L B_L A_H B_H A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 LOWER A<B A>B 4-bit A=B Magnitude Comparator Unigned Number HIGHER A<B A>B 4-bit A=B Magnitude Comparator A < Bin A > Bin A = Bin A < Bout A > Bout A = Bout EE101 Cacading comparator Example 6 ( 4*3 = 12 point) 3 min. All are byte-addreable proceor with logical addre = 32 bit. Fil-in all miing info.l up Data Addre pin D31-D0 A31 - A, BE - BE i860 D63-D0 A31 - A, BE - BE USC_128 D127-D0 A31 - A, BE - BE Min. number of byte-wide bank Shift in addre connection to memory addr pin February 17, :27 am EE457 Quiz - Spring / 8 C Copyright 2012 Gandhi Puvvada

7 7 ( 40 point) 20 min. j, jal, beqal implementation in the ingle cycle CPU: You are familiar with the Spring 2011 quetion and anwer. I have placed the two multiplexor for intercepting and injecting the $31 ID (11111) and the return addre (the PC + 4) for the jal (jump and link) intruction in new location compared to the HW#5a olution jal target; ($31) <= (PC) + 4; (PC) <= incremented_pc[31:28] target 0 2 ; Intruction RegDt ALUSrc Memtoreg RegWrite MemRead MemWrite Branch ALUOp1 ALUop0 Jump Jal beqal R-format lw w X 1 X beq X 0 X jump jal beqal A tated in the Spring 2011 quiz, the beqal i a combination of beq and jal. beqal tand for "branch if equal to branch target addre and alo (only if branching) link the return addre at $31". It i like a conditional call intruction. beqal $r, $rt, word_offet A row and a column are added to the above table to upport thi new intruction. Carry-out the needed modification to the block-diagram on the next page and complete the ignal table above. Note: Make ue of the ignal marked a PCSource on the block diagram. 8 ( = 10 point) 5 min How come, we needed an extra clock (in the form of tate S7) after ALU finihed calculating (in tate S6) the reult of RType intruction, where a for beq intruction, we imply depoited the PC with Target addre then and there (in tate S8) after checking for equality? A temporary regiter MDR (Memory Data Regiter) can be avoided between the memory and the regiter file (though memory read the memory data in a clock/tate and the regiter file conume the data in a ubequent clock) by February 17, :27 am EE457 Quiz - Spring / 8 C Copyright 2012 Gandhi Puvvada

Fall 2010 EE457 Instructor: Gandhi Puvvada Date: 10/1/2010, Friday in SGM123 Name:

Fall 2010 EE457 Instructor: Gandhi Puvvada Date: 10/1/2010, Friday in SGM123 Name: Fall 2010 EE457 Intructor: Gandhi Puvvada Quiz (~ 10%) Date: 10/1/2010, Friday in SGM123 Name: Calculator and Cadence Verilog guide are allowed; Cloed-book, Cloed-note, Time: 12:00-2:15PM Total point: