Avalon Interface. Avalon Interfaces. Open Standard. 7 Interfaces. Streaming Memory Mapped Conduit Tri-state Conduit Interrupt Clock Reset
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2 Avalon Interfaces Open Standard 7 Interfaces Streaming Memory Mapped Conduit Tri-state Conduit Interrupt Clock Reset 2 tj
3 Avalon Interfaces Each interface can include Properties and Parameters Signals Timing Requirments Interfaces can have 0, 1, or many of each item 3 tj
4 Avalon Clock Interface Defines the clock used by the device Input(s) Output(s) Both PLL is an example with multiple outputs Dual Clock FIFO is an example with multiple inputs 4 tj
5 Avalon Clock Interface Clk Sink Input 1 bit wide Provide synchronization for internal block components Properties: clockrate 0 to (2 32 1): 0 allows any frequency Clk Source Output 1 bit wide Properties: clockrate 0 to (2 32 1) associateddirectclock - the clock name that drives this output clockrateknown T/F 5 tj
6 Avalon Reset Interface Reset Sink Input 1 bit wide reset, reset_n normal reset or reset-bar reset_req one clock advanced warning of a reset Properties: associatedclock - the clock name that reset is synchronized to synchronous-edges type of synchronization NONE no synchronization DEASSERT assert is async, deassert is sync BOTH assert and deassert are sync 6 tj
7 Avalon Reset Interface Reset Source Output 1 bit wide reset, reset_n normal reset or reset-bar reset_req one clock advanced warning of a reset Properties: associatedclock - the clock name that reset is synchronized to associateddirectreset- the reset name that drives this output associatedresetsinks reset inputs that will cause a reset output synchronous-edges type of synchronization NONE no synchronization DEASSERT assert is async, deassert is sync BOTH assert and deassert are sync 7 tj
8 Avalon Memory Mapped Interface address 1 64 bits Master Slave Byte address Word aligned Converted to a word address in the slave byteenable(_n) 2,4,8,16,32,64,128 bits Master Slave Enable specific byte lanes 32 bit word -> 4 bytes byteenable = 0b0110 enables bytes 2 and 1 8 tj
9 Avalon Memory Mapped Interface read(_n) read enable Master Slave readdata 8,16,32,64,128,256,512,1025 bits Slave Master write(_n) write enable Master Slave writedata 8,16,32,64,128,256,512,1025 bits Master Slave 9 tj
10 Avalon Memory Mapped Interface response 2 bits Slave Master Optional 00 OKAY 01 reserved 10 slave error transaction failed 11 decode access location restricted or non-existent Lock 1 bit Master Slave Bus hog 10 tj
11 Avalon Memory Mapped Interface waitrequest(_n) 1 bit Slave Master Slave not ready Master must maintain its signal states readdatavalid(_n) 1 bit Slave Master Data is valid (used for bursts) 11 tj
12 Avalon Memory Mapped Interface burstcount 1 11 bits Master Slave Burst 2 n words burstbegintransfer 1 bit Interconnect Slave Burst starting 12 tj
13 Avalon Memory Mapped Interface Fixed slave wait states 13 tj
14 Avalon Memory Mapped Interface waitrequest asserted 14 tj
15 Avalon Memory Mapped Interface pipelined read 2 cycle fixed latency 15 tj
16 Avalon Memory Mapped Interface pipelined read variable cycle latency 16 tj
17 Avalon Memory Mapped Interface Burst write 17 tj
18 Avalon Memory Mapped Interface Burst read 2 masters 18 tj
19 Avalon Interrupt Interface Interrupt Sender Output 1 bit wide irq(_n) Slave Master Properties: associatedaddressablepoint slave interface to access registers associatedclock - the clock name that irq is synchronized to associatedreset - the reset name that irq is synchronized to 19 tj
20 Avalon Interrupt Interface Interrupt Receiver Input 1 32 bits irq Any device that can receive interrupts Properties: associatedaddressablepoint master interface to service interrupts associatedclock - the clock name that irq is synchronized to associatedreset - the reset name that irq is synchronized to 20 tj
21 Avalon Streaming Interface 21 tj
22 Avalon Streaming Interface Definitions Source Sink Backpressure sink can stop flow from source for a period of time Symbol smallest unit that can be transmitted typically a byte Channel The physical or logical interface Beat Single cycle transfer (1 or more symbols) Packet Aggregation of control and data to form a complete transfer 22 tj
23 Avalon Streaming Interface channel bits Source Sink The current active channel data bits Source Sink The data 23 tj
24 Avalon Streaming Interface error bits Source Sink Indicates various error situations ready 1 bit Sink Source Indicates the sink is ready for a transmission valid 1 bit Source Sink Indicates the current transmission is valid 24 tj
25 Avalon Streaming Interface startofpacket 1 bit Source Sink Indicates the beginning of the packet endofpacket 1 bit Source Sink Indicates the end of the packet empty 1 5 bits Source Sink Indicates the number of empty symbols in the packet 25 tj
26 Avalon Streaming Interface Properties associatedclock associatedreset databitspersymbol does not need to be a power of 2 firstsymbolinhighorderbits MS-Symbol first symbolsperbeat # os symbols transferred per beat 26 tj
27 Avalon Streaming Interface Typical interface 64 bit data signal with 16 bitspersymbol Symbol 0 as most significant 27 tj
28 Avalon Streaming Interface databitspersymbol=8 symbolsperbeat=4 beatspercycle=1 28 tj
29 Avalon Streaming Interface No backpressure With backpressure 29 tj
30 Avalon Streaming Interface Packet Transfers 30 tj
31 Avalon Streaming Interface 17 byte packet transfer databitspersymbol=8 symbolsperbeat=4 beatspercycle=1 31 tj
32 Avalon Streaming Interface 17 byte packet transfer databitspersymbol=8 symbolsperbeat=4 beatspercycle=1 32 tj
33 Avalon Conduit Interface In, Out, Bidir Any number of signals 33 tj
34 Avalon Tristate Conduit Interface Allows sharing of signals 2 new signals request grant assert assert access allowed in current clk cycle assert deassert access allowed in next clk cycle deassert assert releases interface after 1 clk deassert deassert nothing 34 tj
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