Today s Agenda Background/Experience Course Information Altera DE2B Board do Overview Introduction to Embedded Systems Design Abstraction Microprocess

Transcription

1 ECEN 4633/5633 Hybrid Embedded Systems Fall 2010 Semester Dr. David Ward

2 Today s Agenda Background/Experience Course Information Altera DE2B Board do Overview Introduction to Embedded Systems Design Abstraction Microprocessors in Embedded Systems Avalon ao Switch Fabric Assignments Questions

3 Course Info Time: Tuesday 5:30 p.m. 9:10 p.m. including lab time Location: ECEE 1B28 (lectures), Lab room 287 (lab) Prerequisites: ECEN 3100 (Digital Logic) and high-level Programming (C/C++) Instructor: David Ward, Office Hours: Tuesday 4:30-5:30 & 9:10-10:10 10:10 PM, ECEE 120 Text: Zainalabedin Navabi: " Embedded Core Design with FPGAs" McGraw-Hill Electronic Engineering, Course web page: ecen5633/ Graduate TA: Mayuresh Varerkar, Office Hours: Thursday 5:30-8:00 PM, Lab room 287

4 Course Info Grading: (20%) HWs; (55%) Lab Exercises; (25%) Project presentation During Final exam period The course is taught using the new Altera DE2 FPGA boards NIOS 2, a 32 bit microcontroller from Altera Altera CAD tools: Quartus 2, SOPC, Nios 2 IDE (Integrated Development Environment). HWs: Due every 2 weeks Four assignments total No late assignments Generally done in groups of two HW assignments and Labs will overlap You must have working program for full credit Lab exercises: Due every week Total six lab exercises

5 Project: Course Info A group project is required (avg. group four persons) Detailed requirements are needed for presentation to the instructor. Complex system analysis will then be performed to identify the overall description and components necessary for implementation. At the end of the semester during the final examination period, a two minute YouTube video demonstration is required along with a 10 minute powerpoint (PPT) description. A formal report is also required along with the source code. Additional information on course web page

6 2010 Project

7 Altera DE2 Board Overview

8 Altera DE2 Board FPGA Cyclone II EP2C35F672C6 with EPCS16 16-Mbit serial configuration device Memory 8-Mbytes SDRAM, 512K SRAM, 4 Mbytes Flash SD Memory slot Displays 16x2 LCD display Eight 7-segment displays

9 Altera DE2 Board Switches and LEDs 18 toggle switches 18 red LEDs 9 green LEDs Four debounced pushbutton switches Clocks 50 MHz crystal for FPGA clock input 27 MHz crystal for video applications External SMA clock input

10 Altera DE2 Board I/O Devices Built-in USB-BlasterTM cable for FPGA configuration 10/100 Ethernet RS232 Video Out (VGA 10-bit DAC) Video In (NTSC/PAL/Multi-format) USB 2.0 (type A and type B) PS/2 mouse or keyboard port Line In/Out, Microphone In (24-bit Audio CODEC) Expansion headers (76 signal pins) Infrared port

11 Introduction to Embedded Systems

12 Big Picture What are embedded systems? Sophisticated functionality. Real-time operation. Low manufacturing cost. Low power. Designed to tight deadlines by g g y small teams.

13 Embedded Systems Embedded d system: any device that includes a programmable computer but is not itself a general-purpose computer, such as a personal computer (PC). Examples: Personal digital assistant (PDA). Printer. Cell phone. Automobile: engine, brakes, etc. Television. Household appliances.

14 Basic Computer System Memory CPU I/O Interface To I/O BUS CPU: I/O: Memory: Bus: Central Processor Unit Input/Output Program and Data Address signals, Control signals, and Data signals

15 Microprocessor-Based System Memory CPU I/O Interface To I/O BUS CPU: Central Processor Unit I/O: Input/Output Microprocessor e.g. Pentium 4 Memory: Program and Data Bus: Address signals, Control signals, and Data signals

16 Microcontroller-Based System Memory CPU I/O Interface To I/O BUS CPU: I/O: Memory: Bus: Central Processor Unit Microcontroller Input/Output e.g. Intel 8051 Program and Data Address signals, Control signals, and Data signals (Although a microcontroller may access external memory as well.)

17 ALTERA DE2 BOARD CYCLONE II INPUT Devices Cyclone II (SOPC) Output Devices C/C++ Language Code

18 Functional Complexity Often have to run sophisticated algorithms or multiple algorithms. Cell phone, laser printer, etc. Often provide complex user interfaces. Must be Reliable and secure Designed to tight deadlines by small teams.

19 Design Process Requirements Specification Conceptualization Analysis Synthesis Verification Documentation Iteration

20 Design Abstraction

21 Design Abstraction Example: Design a system which will complement input A A F(x) Y = A where A and Y are single bit values We can describe this design using a logical Truth Table A Y

22 Levels of Design Abstraction Our goal in ECEN 4633/5633 is physical or hardware implementations of fthe design. Design Specs Design Process 0 1 Vcc1 5 a1 b a2 a3 a4 Hardware GND 0 b2 b3 b In ECEN 4633/5633, we design at several levels of abstraction

23 Levels of Design Abstraction Example: Design a system which will complement input A System Level: A C/C++ Code Y = A C/C++ code: Y = ~A;

24 Levels of Design Abstraction Example: Design a system which will complement input A Behavioral Level: A Not A Y = A VHDL code: Y <= not A;

25 Levels of Design Abstraction Example: Design a system which will complement input A Gate Level: A Y = A Inverter Symbol

26 Levels of Design Abstraction Example: Design a system which will complement input A Circuit Level: PFET Vdd A Y = A NFET CMOS Technology

27 Levels of Design Abstraction Example: Design a system which will complement input A Digital IC Design: Y = A VDD GND A CMOS Technology

28 Levels of Design Abstraction Fabrication Level: P+ P+ N+ N+ NWELL PSUB

29 Summary of Levels System : : Behavioral: C/C++ Logical: Gates Electronic Circuit: Integrated Circuit: Fabrication: VHDL/Verilog Transistors IC Layout IC Processing

30 Microprocessors in Embedded Systems

31 Ordinary microprocessor: CPU plus on-chip cache units. Microcontroller: includes I/O devices, on-board memory. Digital signal processor (DSP): microprocessor optimized for digital signal processing. Hard core vs. soft core. Typical embedded word sizes: 8-bit, 16-bit, 32- bit.

32 Embedded Microprocessors ARM, MIPS, Power PC, Freescale, 8051, X86 Various purposes Networks MIPS Mobile phone ARM dominated Industrial Freescale Coldfire Security 8051 based, Infineon High performance X86, Intel Epic, other VLIW and superscalars

33 Von Neumann CPU Architecture Memory holds data and instructions. Central processing unit (CPU) fetches instructions from memory. Separation between CPU and memory distinguishes programmable computer. CPU registers: program counter (PC) general-purpose registers

34 Harvard Architecture address dt data memory program memory data address instructions CPU PC IR

35 RISC vs. CISC Complex instruction set computer (CISC): many addressing modes most operations can access memory variable length instructions Reduced instruction set computer (RISC): only load/store can access memory fixed-length instructions Instruction set architectures (ISA) characteristics: Fixed vs. variable length. Addressing modes. Number of operands. Types of operands

36 Soft Core Processors Are soft, i.e. specified through field programming g just like programmable logic Shipped as hardware description files, which can be mapped onto FPGA. e.g: Nios 2. Are bundled with software development tools (compiler, simulator, etc.) Offer flexibility as microprocessor parameters can be tuned to the application with tight on-chip interconnection with additional circuitry. Designs can be marketed quickly. You can test and validate many designs quickly without making any specific board; no soldering and no wiring!

37 What is Nios 2? A 32-bit soft core processor from Altera Comes in three flavors: Fast, Standard, Light The three cores trade FPGA area and power consumption for speed of execution. Is a RISC, Harvard Architecture: Simple instructions, separate data and instruction memories. Has 32 levels of interrupts. Uses the Avalon Bus interface (Avalon Switch Fabric) Programs compiled using GNU C/C++ toolchain

38 Nios 2 Architecture

39 Three forms of Nios 2 Nios II/f The Nios II/f fast core is designed for fast performance. As a result, this core presents the most configuration options allowing you to fine-tune the processor for performance. Nios II/s The Nios II/s standard core is designed for small size while maintaining performance. Nios II/e The Nios II/e economy core is designed to achieve the smallest possible core size. As a result, this core has a limited i feature set, and many settings are not available when the Nios II/e core is selected.

40 Selection ect in SOPC (System On a Programmable ab Chip):

41 SOPC System On a Programmable Chip a hardware development tool. Used for integrating various hardware components together like: Microprocessors, such as the Nios II processor Timers Serial communication interfaces: UART, SPI General purpose I/O Digital signal processing (DSP) functions Communications peripherals Interfaces to off-chip devices Memory controllers Buses and bridges Application-specific standard products (ASSP) Application-specific integrated circuits (ASIC) Processors Generates files in Verilog or VHDL which can be added to the Quartus Quatus 2 poject project.

42 Example Nios system:

43 SOPC with Nios II

44 Altera SOPC Builder

45 Avalon Switch Fabric

46 Avalon Switch Fabric Proprietary interconnect specification used with Nios II Principal design goals Low resource utilization for bus logic Simplicity Synchronous operation Transfer Types Slave Transfers Master Transfers Streaming Transfers Latency-Aware Transfers Burst Transfers

47 Avalon Switch Fabric Custom-Generated for Peripherals Contingencies are on a Per-Peripheral Peripheral Basis System is Not Burdened by Bus Complexity SOPC Builder Automatically Generates Arbitration Address Decoding Data Path Multiplexing Bus Sizing Wait-State Generation Interrupts

48 Avalon Master Ports Initiate Transfers with Avalon Switch Fabric Transfer Types Fundamental Read Fundamental Write All Avalon Masters Must Honor a waitrequest signal Transfer Properties Latency Streaming Burst

49 Avalon Slave Ports Respond to Transfer Requests from Avalon Switch Fabric Transfer Types Fundamental Read Fundamental Write Transfer Properties Wait States Latency Streaming Burst

50 Slave Read Transfer clk A B C D E address,be_n address, be_n readn chipselect readdata readdata

51 Slave Write Transfer clk address,be_n writedata A B C D address, be_n writedata writen chipselect

52 Assignments

53 Assigments Suggested Reading Chapters 1-3 in textbook Should be a quick review DE2_UserManual on Can be used as a quick reference HW # 1, due by midnight September 3, 2010 Lab #1, due by August 31 (at the start of lab)

54 Questions?