OpenPiton in Action. Princeton University. OpenPit
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1 OpenPiton in Action Princeton University OpenPit
2 FPGA Prototyping 2
3 Supported Development Boards Boards supported by toolchain: Digilent Genesys2 Xilinx VC707 Digilent NexysVideo Digilent Nexys4DDR* * doesn t have DDR controller and FPU 3
4 Comparison of Supported Boards Development Board, FPGA name, Part Core Clock (1 core) Max # of Cores DDR Type, Size, Data Width Price (nonacademic/ academic) Xilinx VC707 Virtex-7 XC7VX485T-2FFG1761C 60 MHz 3 DDR3 1 GB 64 bits $3,495 Digilent Genesys2 Kintex-7 XC7K325T-2FFG900C 67 MHz 2 DDR3 1GB 32 bits $1,299/ $600 Digilent NexysVideo Artix-7 XC7A200T-1SBG484C 30 MHz 1 DDR3 512MB 16 bits $490/ $250 Digilent Nexys 4 DDR Artix-7 XC7A100T-ACSG324C 30 MHz 1 DDR2 128MiB 16 bits $320/ $160 4
5 IO_CTRL_TOP Prototype Architecture DDR controller*: Xilinx s MIG 7 IP core Configurable data width Used as main memory Wishbone SD Master*: Up to 32GB SD/SDHC cards Storage for HV/OS/tests UART DRAM SDHC Master UART: Terminal I/O Loading of assembly test (DMW - Direct Memory Write from a host) ETH OpenPiton Core Ethernet controller*: Xilinx s Ethernet Lite MAC IP Core Driver from Linux kernel 100 Mb/s Switches, LEDs Digilent Genesys2 *optional 5
6 Demo 8
7 Setup for Hands-on with FPGA 9
8 Setting Up Terminal (MAC) 10
9 11
10 Setting Up Terminal Find serial device: Windows: Device Manager Linux: /dev/ Unplug/Plug back USB cable to determine the right one 12
11 Setting Up Terminal (Windows, Linux) Serial Line: /dev/ttyusbx or COMX, where X is a number depending on your system Speed:
12 Setting up Your FPGA Board GO! 14
13 Booting Linux After ~10s 15
14 FPGA Linux Boot After ~2min systemd starts 16
15 Coffee Break 17
16 FPGA Linux Boot 18
17 Hands on: Login to the System Login: Password: root root 19
18 Suggested Configurations BRAM with hardwired test DRAM memory controller SD card controller BRAM_TEST SD with OS + Eth UART DMW to DDR UART Ethernet Lite MAC UART support for test streaming 20
19 Tools protosyn All encompassing tool for creation of FPGA project and generating programming file board type, design, config opt protosyn pitonstream Tool for running assembly tests on FPGA.xpr.bit board type, asm test list pitonstream.ustr Sources are located at piton/tools/src/proto/ 21
20 RTL protosyn Flow Legend Control Flow Data Flow pyv preprocessor Sims script Vivado input/output files flow step conditions *.v.pyv -> *tmp.v bram test? YES sims build sims run NO mem.image sims.log test_proto.coe mapping test to BRAM IP cfg (.xci), constraints (.cdc), defines create project? YES project creation NO.xpr.bit,.ltx.xpr implement? YES synthesis mapping, placing, routing, bitstream generation, STA NO 22
21 Bringing up Network Put a MAC from your board! 23
22 Running protosyn more options are in FPGA manual 24
23 Example protosyn run 25
24 FPGA Flow Runtimes System including DDR controller ~1.5 hour including IP generation ~40 mins excluding IP generation 26
25 FPGA Flow Outputs 27
26 FPGA Flow Outputs 28
27 FPGA Flow Outputs 29
28 Example pitonstream Run 30
29 Writing OS Image to SD Card (Windows) 31
30 Writing OS Image to SD Card (Windows) 32
31 Writing OS Image to SD Card (Windows) 33
32 Hands-on with FPGA 34
33 Running Tetris on OpenPiton 35
34 Browsing OpenPiton web page on OpenPiton 36
35 Backup Slides 37
36 Opening FPGA Design 38
37 Opening FPGA Design 39
38 FPGA Programming 40
39 FPGA Programming 41
40 FPGA Programming 42
41 FPGA Programming 43
42 FPGA Programming 44
43 FPGA Programming 45
44 FPGA Programming 46
45 FPGA Programming 47
46 FPGA Programming 48
47 Synthesizing the Hello, World! Assembly Test download tar.gz of the release extract archive and set up environment run protosyn -b genesys2 --no-ddr --bram-test uart-hello-world.s wait until bit file is generated open Hardware Manager in Vivado or Vivado Lab Edition connected to Genesys2 board open a target and program the board with a generated.bit file open serial port on host machine press reset 49
48 Booting Debian Linux and Playing Tetris download tar.gz archive of OpenPiton release extract it and set up your environment and tools run protosyn -b genesys2 wait until bit file is generated open Hardware Manager in Vivado or Vivado Lab Edition connected to Genesys2 board open a target and program the board with a generated.bit file write.bin file with OpenBoot and OS image on SD card insert the SD card into the board and press reset wait for Open Boot to start OK boot prompt print boot Linux command in OK boot prompt wait for Linux to boot use root both as login and password print tetris in Linux prompt and play the game! 50
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