Overview. Leader Election Protocol. Dynamic Voltage Scaling. Optimal Reconfiguration of FPGA. Memory Interface. UCb

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Myrtle Morgan Anthony
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1 APPLICATIONS UC b

2 Overview Leader Election Protocol Dynamic Voltage Scaling Optimal Reconfiguration of FPGA Memory Interface

3 Leader Election Protocol UC b

4 Leader Election Protocol by Leslie Lamport

5 Leader Election (leader,hops) (2,0) (1,0) 2 1 (0,0) 0 3 (3,0)

6 Timeout (2,0) (1,0) 2 1 (0,0) 0 3 (3,0)

7 Flooding (2,0) (1,2,1,0) (1,0) 2 1 (0,0) 0 (1,0,1,0) (1,3,1,0) 3 (3,0) (src,dst,leader,hops)

8 Flooding (2,0) (1,2,1,0) (1,0) 2 1 (0,0) 0 (1,0,1,0) 3 (3,0) (1,3,1,0)

9 Flooding (2,0) (1,2,1,0) (1,0) 2 1 (0,0) 0 (1,0,1,0) 3 (1,1)

10 Forwarding (2,0) (1,2,1,0) (1,0) 2 1 (0,0) 0 (1,0,1,0) (3,2,1,1) 3 (1,1)

11 Forwarding (2,0) (1,2,1,0) (1,0) 2 1 (0,0) 0 (1,0,1,0) (3,2,1,1) 3 (1,1)

12 Forwarding (1,1) (1,0) 2 (2,0,1,1) (0,0) 0 (2,3,1,1) (1,0,1,0) 1 (3,2,1,1) 3 (1,1)

13 Leader Election (1,1) (1,0) 2 1 (0,0) 0 3 (1,1)

14 Leader Election (1,1) (1,0) 2 1 (0,0) 0 3 (1,1)

15 Leader Election (0,1) (0,1) 2 1 (0,0) 0 3 (0,2)

16 Variable timeout timeout timer hops time Timeout Timeout Update received Update received Update received

17 Leader Election Claim to be verified Correct leader is known at a node i after t(i) = Δ TO + Δ TDELAY + d i Δ MDELAY A model checking problem for all i. IMP ² >t(i) l(i)=l(i)

fine. As As expected, expected, it's it's 2 2 or or 3 3 orders orders of of magnitude magnitude faster faster than than TLC.

18 Modelling (RT) protocols Users Protocol stacks Medium All, All, Thanks Thanks for for the the spec. spec. It It seems seems to to run run fine. fine. As As expected, expected, it's it's 2 2 or or 3 3 orders orders of of magnitude magnitude faster faster than than TLC. TLC. I'm I'm wondering wondering if if your your algorithms algorithms could could be be used used for for checking checking specs specs written written in in a a higher higher level level language language like like TLA+. TLA+.

19 Modelling (RT) protocols Users Protocol stacks

20 Modelling (RT) protocols Users Protocol stacks Messages

21 Modelling the election protocol Per process dist i : N leader i : Node timeout i : N Message src: Node dst: Node leader: Node hopss: N

22 Global Declaration

23 Message

24 Node[id]

25 Local Declarations (Node[id])

26 Optimisations Reducing the number of active variables If variable is never used until next reset, then the value does not matter. Symmetry of message processes The message processes are symmetric: It does not matter which is used to transfer a message.

27 Dynamic Voltage Scaling UC b

28 Performance vs Ressource-Efficiency? Consumer constantly demand better functionality, flexibility, availability,.. increase in resources needed: Time Energy Memory Bandwidth.. Application of CUPPAAL to modeling, analysis and synthesis of resourceefficient schedules for realtime systems.

29 Power Management Dynamic Voltage Scaling

30 Energy in Processor Power consumption mainly by dynamic power energy A non-experts understanding of CMOS P E dynamic dynamic = C L pr. cycle V = 2 dd C L f clk V 2 dd Supply voltage reduction => decreased frequency delay V dd f clk ~ V ( α -1) dd ; α > 1 V dd We may miss deadlines

31 Task Scheduling utilization of CPU P(i), [E(i), L(i)],.. : period or earliest/latest arrival or.. for T i C(i): execution time for T i D(i): deadline for T i T 1 T 2 ready done Scheduler T n stop run T 2 is running { T 4, T 1, T 3 } ready ordered according to some given priority: (e.g. Fixed Priority, Earliest Deadline,..)

32 Modeling Task T 1 1 T 2 2 T n n ready done stop run Scheduler

33 Modeling Scheduler T 1 1 T 2 2 T n n ready done stop run Scheduler

34 Modeling Queue T 1 1 T 2 2 T n n ready done stop run Scheduler

35 Schedulability = Safety Property May be extended with preemption (Task0.Error or Task1.Error or ) A (Task0.Error or Task1.Error or )

36 Energy Optimal Scheduling Using Priced Timed Automata T 1 1 T 2 2 ready done Scheduler T n n stop run F:=?? ; V:=?? Choose Scaling/Cost (Freq/Voltage) C

37 Energy Optimal Scheduling = Optimal Infinite Path Accumulated cost σ c 1 c 2 c 3 c n t 1 t 2 t 3 t n (Task0.Error or Task1.Error or ) Accumulated time Value of path σ: val(σ) = lim n c n /t n Optimal Schedule σ * : val(σ * )= inf σ val(σ)

38 Energy Optimal Scheduling = Optimal Infinite Path Accumulated cost σ c 1 c 2 c 3 c n t 1 t 2 t 3 t n (Task0.Error or Task1.Error or ) Accumulated time Value of path σ: val(σ) = lim n c n /t n THEOREM: σ * is is computable Bouyer, Brinksma, Larsen 03 Optimal Schedule σ * : val(σ * )= inf σ val(σ)

Approximate Optimal Schedule T<N T<N X X

39 Approximate Optimal Schedule T<N T<N X X T<N X Optimal infinite schedule modulo cost-horizon T>=N T>=N C=M C=M C=M C=M E[] (not (Task0.Error or Task1.Error or Task2.Error) and (cost>=m imply time >= N)) = E[] φ(m,n) σ ² [] φ(m,n) imply val(σ) M/N

40 Preliminary Results P 1 =D 1 =32 C 1 =6 P 2 =D 2 =48 C 2 =18 P 3 =D 3 =64 C 3 =12 EDF w preemption no DVS: avr.: 48

41 Preliminary Results Cost horizon: 2,000 P 1 =D 1 =32 C 1 =6 P 2 =D 2 =48 C 2 =18 P 3 =D 3 =64 C 3 =12 EDF w preemption w DVS: avr.: 43.37

42 Optimal Reconfiguration of FPGA Utilizing new features of UPPAAL 4.0 User-defined functions Types & Select Due to Jacob I. Rasmussen

43 Field Programmable Gate Array Informationsteknologi

44 The Problem Informationsteknologi

45 The Problem Informationsteknologi

46 Example Informationsteknologi

47 Example Informationsteknologi

48 Example Informationsteknologi

49 Example 1 Informationsteknologi

50 Example 1 Informationsteknologi

51 UPPAAL Model Informationsteknologi

52 UPPAAL Model Informationsteknologi

53 UPPAAL Model Informationsteknologi

54 UPPAAL Model Informationsteknologi

55 Memory Interface UC b

Memory Management Radar Video Processing Subsystem

56 Memory Management Radar Video Processing Subsystem Advanced Noise Reduction Techniques Costal Surveillance e 0,5 e 0,4 e 0,3 e 0,2 e 2,4 e 1,2 e 1,3 e 1,4 e 2,2 e 1,5 e 2,3 e 2,5 e e 3,5 3,4 e e3,3 3, GHz GHz Combiner (VP3) echo Frequency Diversity Airport Surveillance Sweep Integration combiner

57 Input A 8 (100MHz) Input B 8 (100 MHz) Buffer 1 1 Kbytes Buffer 2 1 Kbytes A' 8 (100MHz) Buffer bytes Adder 1 S' 16 (100 MHz) Buffer 4 S = A + S' - A' 2 Kbytes 16 (100 MHz) 8 (100MHz) Buffer (200 MHz) B B' 8 (100MHz) 512 bytes Buffer bytes SDRAM Adder 2 T' Buffer 7 T = B + T' - B' 16 (100 MHz) 2 Kbytes T 16 (100 MHz) S Buffer 8 2 Kbytes Buffer 9 2 Kbytes Output S Output T Arbiter

58 Input A 8 (100MHz) Input B 8 (100 MHz) Buffer 1 1 Kbytes A' 8 (100MHz) Buffer 2 1 Kbytes Buffer 3 A single buffer 512 bytes Adder 1 S' 16 (100 MHz) Buffer 4 S = A + S' - A' 2 Kbytes 16 (100 MHz) 8 (100MHz) Buffer (200 MHz) B B' 8 (100MHz) 512 bytes Buffer bytes SDRAM Adder 2 T' Buffer 7 T = B + T' - B' 16 (100 MHz) 2 Kbytes T 16 (100 MHz) S Buffer 8 2 Kbytes Buffer 9 2 Kbytes Output S Output T Arbiter

59 Input A 8 (100MHz) Input B 8 (100 MHz) broadcast chan tick; const CYCLE 10; Buffer 1 1 Kbytes // 100MHz = 10ns cycle Buffer 2 1 Kbytes A' 8 (100MHz) Buffer bytes Adder 1 S' 16 (100 MHz) Buffer 4 S = A + S' - A' 2 Kbytes 16 (100 MHz) 8 (100MHz) Buffer (200 MHz) Clock B B' 8 (100MHz) 512 bytes Buffer bytes SDRAM Adder 2 T' Buffer 7 T = B + T' - B' 16 (100 MHz) 2 Kbytes T 16 (100 MHz) S Buffer 8 2 Kbytes Buffer 9 2 Kbytes Output S Output T Arbiter

60 Input A 8 (100MHz) Input B 8 (100 MHz) Buffer 1 Buffer 2 1 Kbytes const REGSIZE 64; // 64 byte = 512 bits 1 Kbytes int[-4,1028] buffer; int[0,64] register A' 8 (100MHz) Buffer bytes Adder 1 S' 16 (100 MHz) Buffer 4 S = A + S' - A' 2 Kbytes 16 (100 MHz) 8 (100MHz) Buffer (200 MHz) Input Buffer B B' 8 (100MHz) 512 bytes Buffer bytes SDRAM Adder 2 T' T = B + T' - B' 16 (100 MHz) T 16 (100 MHz) S Buffer 7 2 Kbytes Buffer 8 2 Kbytes Buffer 9 2 Kbytes Input Register Output S Output T Arbiter

61 Input A 8 (100MHz) Input B 8 (100 MHz) Buffer 1 1 Kbytes A' Buffer 2 1 Kbytes const REFRESH_PERIOD 15525; 8 (100MHz) Buffer 3 const REFRESH_TIME 100; 512 bytes Adder 1 S' 16 (100 MHz) Buffer 4 S = A + S' - A' 2 Kbytes 16 (100 MHz) 8 (100MHz) Buffer (200 MHz) B B' 8 (100MHz) 512 bytes Buffer bytes SDRAM Adder 2 T' Buffer 7 T = B + T' - B' 16 (100 MHz) 2 Kbytes T 16 (100 MHz) Buffer 8 2 Kbytes Memory (-ies) S Buffer 9 2 Kbytes Output S Output T Arbiter

62 Input A 8 (100MHz) Input B 8 (100 MHz) Buffer 1 1 Kbytes Buffer 2 1 Kbytes A' 8 (100MHz) Buffer bytes Adder 1 S' 16 (100 MHz) Buffer 4 S = A + S' - A' 2 Kbytes 16 (100 MHz) 8 (100MHz) Buffer (200 MHz) B B' 8 (100MHz) 512 bytes Buffer bytes SDRAM Adder 2 T' Buffer 7 T = B + T' - B' 16 (100 MHz) 2 Kbytes T 16 (100 MHz) Buffer 8 2 Kbytes Arbiter (round robin) S Buffer 9 2 Kbytes Output S Output T Arbiter

Statistical Model Checking in UPPAAL

Statistical Model Checking in UPPAAL Alexandre David, Kim G. Larsen, Marius Mikucionis Axel Legay, Wang Zheng, Peter Bulychev, Jonas van Vliet, Danny Poulsen, Dehui Du, Guangyuan Li CAV 11, PDMC 11,FORMATS