Optimization of Phase- Locked Loop Circuits via Geometric Programming

Transcription

1 Optimization of Phase- Locked Loop Circuits via Geometric Programming D. Colleran, C. Portmann, A. Hassibi, C. Crusius, S. S. Mohan, S. Boyd, T. H. Lee, and M. Hershenson

2 Outline Motivation Geometric programming (GP) GP compatible transistor models Clock generation PLL topology PLL design in GP form Silicon results

3 Simulation-based methods W1 = 1 W2 = 2 : : L8 = 1 General purpose Long design cycles Needs circuit expert Needs optim. expert Power = 1 Gain = 500

4 Geometric programming-based method R L V dd R L Gain = f 1 (R,M 1, I b ) Gain > 100 BW > 10MHz 0.13µm CMOS : : : M 1 M 2 BW = f n (R,M 1,I b ) Ib Numerical GP Optimization Solver M1.gm=f 1 (W,L, ) : : : M1.Cgs= f n (W,L, )

5 Outline Motivation Geometric programming (GP) GP compatible transistor models Clock generation PLL topology PLL design in GP form Silicon results

6 Geometric programming A monomial function g(x) has the form g α α 2 α n ( x) = cx 1 x ( c > 0) 1 A posynomial function f(x) is a sum of monomials For example, Geometric program (GP) is minimize subject to 2 x n f ( x ) = 2 x + x x 2 f f g 0 ( i i x) x 0 1 x. 5 ( x) 1 i = 1,..., m (x) = 1 i = 1,..., p GPs can be easily transformed into convex problem 1 3

7 Solving GP s New interior point methods for GP are extremely fast find globally optimal solution or provide proof of infeasibility are independent of starting point For PLL synthesis: 40k optimization variables and 150k constraints takes ~90 minutes on 2GHz PC

8 Outline Motivation Geometric programming (GP) GP compatible transistor models Clock generation PLL topology PLL design in GP form Silicon results

9 GP electrical models G D I D S Complex GP models can be developed including shortchannel effects, finite output impedance, etc, e.g.,

10 GP models Id vs. Vds, 0.18µm 1.5 Id (ma) Vds (V)

11 GP physical models Posynomial expressions for Width and height, e.g., AD, AS, PD & PS, e.g., Placement and Routing Symmetry Constraints Mirroring Nets Net Matching Alignment Capacitance Constraints Shielding EM/IR drop considerations Dummy poly for matching and STI

12 Outline Motivation Geometric programming (GP) GP compatible transistor models Clock generation PLL topology PLL design in GP form Silicon results

13 PLL topology Charge pump PLL with low power programmable dividers (12 bit, >2GHz) Variables include device dimensions (W,L) and # of ring oscillator stages (S)

14 Charge pump topology Example current mirror equalities (monomial):

15 VCO topology Example saturation margin inequalities (posynomial):

16 Outline Motivation Geometric programming (GP) GP compatible transistor models Clock generation PLL topology PLL design in GP form Silicon results

17 Second-order PLL system-level equations, in monomial form

18 Power consumption (posynomial)

19 Accumulated jitter, T aj (posynomial) σ j κ t 0.5 From McNeil (JSSC 1997): Using Hajimiri s phase noise model (JSSC 1998):

20 Static phase error, T err (posynomial) G D S I D Using Pelgrom s mismatch model (JSSC 1989 ):

21 Outline Motivation Geometric programming (GP) GP compatible transistor models Clock generation PLL topology PLL design in GP form Silicon results

22 GP vs. Silicon 0.18um PLL arrays # Fref [MHz] Fvco [MHz] T pj [ps] Φ e [ps] Power [mw] GP Meas T aj [ps] GP Meas Good agreement between GP and silicon meas.

23 GP vs. Silicon 0.13um PLL arrays # Fref [MHz] Fvco [MHz] T pj [ps] Φ e [ps] Power [mw] GP Meas T aj [ps] GP Meas Good agreement between GP and silicon meas.

24 Acc. jitter vs. F vco trade-off analysis Acc. jitter (ps) VCO frequency range (MHz)

25 Power vs. F vco trade-off analysis 35 Power (mw) VCO frequency range (MHz)

26 Automated design does not translate into performance degradation PLL Fref Fvco Taj,noise Tpj,noise # [MHz] [MHz] [ps] [ps]-[%tvco/%vdd] Simulated 0.13µm, worst case PVT (FF, -40C or 125C) with 10% step on Vdd Comparison to Literature 0.10 %Tvco/%Vdd for 2.5V, MHz PLL (M. Mansuri, ISSCC 2003) 0.08 %Tvco/%Vdd for 2.0V, MHz PLL with voltage regulator (V. Van Kaenel, JSSC 1998) Room temperature with 10% step on Vdd

27 Conclusions First demonstration of fully-automated PLL design, from specification to GDSII PLL design problem cast in GP form reduces design time from weeks to hours Measured 0.18 µm and 0.13 µm CMOS PLL arrays agree with GP predictions (e.g. 1.9 GHz, 11 mw PLL with 5.8 ps long-term jitter) Robust, systematic, and efficient PLL design