Atmel s s AT94K Series Field Programmable System Level Integrated Circuit (FPSLIC)

Transcription

1 Atmel s s AT94K Series Field Programmable System Level Integrated Circuit (FPSLIC) Embedded Systems Based Built-In Self-Test and Diagnosis of the FPGA Core Slide 1 Embedded Systems Lecture 1/19/08

2 System-On-Chip Issues $250K+ NRE CES note: these are old numbers much higher now $100K+ design tools CES note: these are old numbers much higher now Large volume requirements Custom product ASSP Logic Clock Analogue NVM CPU Long design time High risk FPGA Glue Logic Power Management Memory SRAM IP issues (availability, cost implementation) >> System level integration not viable for most customers Slide 2 Embedded Systems Lecture 1/19/08

3 Field Programmable System Level Integrated Circuit reducing power consumption MCU MEM MEM MCU FPGA ASIC/ FPGA Most of power used in I/O pads Power is reduced by more than 50% Standby <100uA Active 2-3mA/MHz Discrete Solution Slide 3 Embedded Systems Lecture 1/19/08 Monolithic Solution

4 Atmel Programmable SLi Roadmap ASIC FPSLIC TM TM with with Embedded AT40K FPGA core Features AT40K AT40K with with RISC RISC uc uc AVR AVR TM TM FPSLIC FPSLIC TM TM AT40KxxAL AT40KxxAL Low Low $ AT40KxxAV AT40KxxAV Low Low $ AT40K AT40K with with ARM ARM ARM ARM FPSLIC FPSLIC TM TM AT40KxxAX AT40KxxAX Low Low $ 1.8V 0.18u 1.8V 0.12u 3.3V 0.35u Slide 4 Embedded Systems Lecture 1/19/08

5 User-Defined Logic Spectrum Custom ASIC Cell based ASIC Gate Array Density FPGA FPSLIC CPLD PAL- Type ATF22V10 ATF16V8 ATF20V8 ATV2500B ATF1500 Fam ATV750B AT6000 AT40K AT94K ATL25 Series ATL35 Series ATL50 Series ATL60 Series Macrocells 0.25, 0.35, 0.5, 0.6 Analog / Digital Analog / Digital/ NV Memory, RF Decoders, Glue Logic State machines, Timing, Control RAM/Logic, Computing, Co-processing Programmable SLI with AVR High Volume/Low Cost System Level Integration Total Customization Very High Volume Slide 5 Embedded Systems Lecture 1/19/08

6 Atmel s Flash MCU Families Price vs Performance Performance Engine Control Laser Printer Internet ARM-7 Settop Boxes Disk Drives Cellphones Auto Elect. Appliances Keyless Entry AVR C51 Price $1 $2 $5 $10 $20 Slide 6 Embedded Systems Lecture 1/19/08

7 Monolithic SRAM Based FPSLIC Up to 36K bytes of SRAM Configurable SRAM 8 Bit RISC MCU AT40K FPGA 20 MIPS* - 8bit RISC MCU 120+ instructions *30 MIPS version available Q From 5K to 40K gates FPGA Slide 7 Embedded Systems Lecture 1/19/08

8 Designer Defined Program and Data SRAM Allocation Designer Allocated Memory in 4Kbyte chunks 10K * Words Instruction (x 16) 20Kbytes Program Memory 2K x 8 2K x 8 2K x 8 2K x 8 2Kx 8 2K x 8 Fixed 4K Byte for Data RAM Memory partition is user defined during development Easy to trade-off Program and Data SRAM * 2K Words (x16) for µfpslic (AT94K05) Slide 8 Embedded Systems Lecture 1/19/08

9 Internal Data SRAM Access Data SRAM (DPRAM) 4K byte up to 16Kbyte AVR-Add[15:0] Avr-Data[7:0] AVR-R/W AVR-Clk FPGA-Add[15:0] FPGA-Data[7:0] FPGA-R/W FPGA-Clk 8 Bit RISC MCU AT40K FPGA True Dual Port Access AVR can disable writing from FPGA Slide 9 Embedded Systems Lecture 1/19/08

10 FPSLIC Embedded Blocks Configurable SRAM SRAM interface 8 Bit RISC MCU AVR/AT40K interface AT40K FPGA Software configurable interface between blocks already implemented Pre-implemented Interface blocks save FPGA gates Slide 10 Embedded Systems Lecture 1/19/08

11 Internal I/O space and Interrupts 8 Bit RISC MCU I/O select[15:0] R/W Data[7:0] Int[15:0] AT40K FPGA Write: ldi r16,0x00 ldi r17,0x02 out FISCR,r16 ; I/O select 0 out FISUA,r17 ; r17 data on the bus Data[7:0] I/Oselect[0] W 02 Slide 11 Embedded Systems Lecture 1/19/08

12 AVR-FPSLIC Family 5K, 10K and 40K gate AT40K FPGA options AVR microcontroller 120+ instructions Device Array Size 4-LUTs FFs FPGA Gates AT94K05 16x K AT94K10 24x K AT94K40 48x48 2,304 40K FreeRAMs SRAM bits 16 RAMs 2048 bits 36 RAMs 4096 bits 144 RAMs bits FPGA I/O 96 max 192 max 384 max Program Memory Data SRAM 4K 16K Bytes/ 4K-16K Bytes 20K 32K Bytes/ 4K-16K Bytes 20K 32K Bytes/ 4K-16K Bytes Slide 12 Embedded Systems Lecture 1/19/08

13 AVR Harvard architecture 32 8-bit regs ALU w/multiplier 120+ instructions Slide 13 Embedded Systems Lecture 1/19/08

14 FPSLIC - Partial Reconfiguration using AVR CacheLogic T M Software Application Data/Keys 3 DES RSA 8 Bit RISC MCU X[7:0] Y[7:0] Z[7:0] 32 bits Y 3 RSA DES D[7:0] write Z X Hardware implemented for the AVR to control partial reconfiguration Enable Hardware context switching Slide 14 Embedded Systems Lecture 1/19/08

15 Cache Logic Mode Mode designed for CacheLogic applications Device treated as an SRAM by the system Microprocessor treats FPGA as memory mapped I/O. Simple 24 bit Address and 8 bit Data structure. MSB LSB X Address Y Address Tag Z Address Data 8 Bits 8 Bits 4 Bits 4 Bits 8 Bits 32 Bit word defines address and data Information for one byte per clock cycle 31 0 Slide 15 Embedded Systems Lecture 1/19/08

16 AT40K Logical Memory Map Core Cells (PLBs) Vertical Repeaters Horizontal Repeaters North/South I/O And so on... TAG Addressed PAGES 4 Dimensional Memory Map Tag Defines Page being written X,Y Define Array Location Z defines which byte at a given X,Y Location is written Cell Y Location Z Z BYTE n BYTE... BYTE 2 BYTE 1 BYTE 0 Cell 0,1 BYTE n BYTE... BYTE 2 BYTE 1 BYTE 0 Slide 16 Embedded Systems Lecture 1/19/08 Z Z BYTE n BYTE... BYTE 2 BYTE 1 BYTE 0 Cell 1,1 BYTE n BYTE... BYTE 2 BYTE 1 BYTE 0 Cell 0,0 Cell 1,0 Cell X Location