ECE 437 Computer Architecture and Organization Lab 6: Programming RAM and ROM Due: Thursday, November 3

Transcription

1 Objectives: ECE 437 Computer Architecture and Organization Lab 6: Programming RAM and ROM Due: Thursday, November 3 Build Instruction Memory and Data Memory What to hand in: Your implementation source files. Submit your homework through the homework submission website. (Please do not to my departmental address.) Note: This is a group lab and you should work with your project partner. In the pipelined processor design, you need to use RAM on the DE2 boards for instruction memory and data memory, respectively. The following documents on the project website are helpful to access RAM. RAM Megafunction User Guide Using the SDRAM Memory on Altera s DE2 Board with VHDL or Verilog Design 1. The RAM Interface The DE2 board provides three types of memory, including 512-Kbyte SRAM, 8-Mbyte SDRAM and 4- Mbyte Flash memory. The SRAM is organized as 256K 16bits, the SDRAM is organized as 1M 16bits 4 banks, and the Flash memory is 8-bit data bus. The signals needed to communicate with this chip are shown in the figure below. All of the signals, except the clock, can be provided by the SDRAM Controller. The clock signal is provided separately. It has to meet the clock-skew requirements. Note that some signals are active low, which is denoted by the suffix N. 2. Using LPM to Access SDRAM and ROM You can use altsyncram LPM provide in Quartus II to access the RAM on the DE2 board. (Quartus II also provides lpm_ram_dq and lpm_rom functions, but they are only for backward compatibility. The altsyncram megafunction is recommended by Altera.) The following briefly summarizes the procedure of using altsyncram. 1

2 In this project, you need to create a new Quartus II projects to access. The target FPGA chip on the DE2 board is Cyclone II EP2C35F672C6. The tutorial Using Library Modules in VHDL Designs describes the usage of MegaWizard to build a desired LPM module. i. In the Memory Compiler category, you can find RAM: 1-PORT LPM ii. Select VHDL or Verilog HDL as the type of output file to create iii. Give the file the name ramlpm.vhd (for VHDL) or ramlpm.v (for verilog) iv. In the next windows, you can customize the RAM configurations, such as the width, clock. You can also initiate the values of RAM using a MIF file. The format of MIF is given in this handout. 2

3 The following notes are copied from Atlera s RAM Megafunction User Guide. The RAM: 1-PORT MegaWizard Plug-In Manager allows you to specify either of two clocking modes: a single clock mode or a dual clock (input/output) mode. In single clock mode, the read and write operations are synchronous with the same clock. In the Stratix and Cyclone series of devices, a single clock with a clock enable controls all registers of the memory block. Dual clock (input/output) mode operates with two independent clocks: inclock (input clock for write operation) and outclock (output clock for read operation). The input clock controls all registers related to the data input to the memory block, including data, address, byte enables, read enables, and write enables. The output clock controls the data output registers. Synchronous write operations into the memory block use the address[] and data[] ports, which are triggered by the rising edge of the inclock while the we (write enable) port is 3

4 enabled. For asynchronous operation, the address[] and data[] signals must be valid at both edges of the write enable signal. Ideally, the values on the data and address lines should not be changed while the we port is active. 3. Memory Initialization Format (MIF) The data of the RAM and Rom can be initialized according to an ASCII text file named Memory Initialization Format (with the extension.mif). The following gives two example MIF files. DEPTH = 256; % Memory depth and width are required % WIDTH = 16; % Enter a decimal number % ADDRESS _RADIX = HEX; % Address and value radixes are optional % DATA - RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % % otherwise specified, radixes = HEX % -- Specify initial data values for memory, format is address : data CONTENT BEGIN [00..FF] : 0000; % Range - Every address from 00 to FF = 0000 % -- Computer Program for A = B + C 00 : 0210; % LOAD A with MEM(10) % 01 : 0011; % ADD MEM(11) to A % 02 : 0112; % STORE A in MEM(12) % 03 : 0212; % LOAD A with MEM(12) check for new value of FFFF % 04 : 0304; % JUMP to 04 (loop forever) % 10 : AAAA; % Data Value of B % 11 : 5555; % Data Value of C % 12 : 0000; % Data Value of A - should be FFFF after running program $ END; Note: If multiple values are specified for the same address, only the last value is used. 4

5 4. Lab Instructions and Requirements 1. Build the Data Memory. a. You should be able to read and write SDRAM by using RAM: 1-PORT MegaWizard Plug-In Manager. The output of SDRAM is 32 bits. The SDRAM will be used as the data memory in the project. Note that we are using 32-bit wide data memory to simplify the design since we will use load word (lw). As a result, in one cycle, we can get the data out. b. In MegaWizard, both the input and output can be registered or not registered. First of all, make both registered and test it on the board. Then make the output not registered and test it again on the board. Find out the difference between registered and not registered. c. In MegaWizard, you can use single clock or dual clocks. The dual clocks have separated clocks for inputs and outputs. Make the right choice. d. Initialize the data memory as the following. Please note the data memory address in MIPS code is in terms of bytes, not words. Test your design on the Altera DE2 board using the display and control specification given at the end of this handout. e. Please note that in the MIPS programs, the data segment starts at 0x Since the data size of our test programs is small, thus you can ignore the most significant four bits in the data address. Address Code 1 0x x x x x x x c 0x x x x x x x x c 0x x x x x A 11 0x c 0x B 12 0x x C 13 0x x D 14 0x x E 15 0x c 0x F 16 0x x

6 2. Build the Instruction Memory. a. In the project built in Step 1, add a new component that can read ROM by using ROM: 1- PORT MegaWizard Plug-In Manager. The output of ROM is 32 bits. The ROM will be used as the instruction memory in the project. b. In MegaWizard, both the input and output can be registered or not registered. You need to make the right choice for both input and output. c. In MegaWizard, you can use single clock or dual clocks. The dual clocks have separated clocks for inputs and outputs. Make the right choice. d. Initialize the instruction memory as the following. Please note the instruction memory address in MIPS code is in terms of bytes, not words. Test your design on the Altera DE2 board using the display and control specification given at the end of this handout. e. Please note that in the MIPS programs, the instruction segment starts at 0x Since the data size of our test programs is small, thus you can ignore the most significant 12 bits in the data address. Instruction Address Code 1 add $3, $2, $1 0x x addu $3, $2, $1 0x x sub $3, $2, $1 0x x subu $3, $2, $1 0x c 0x and $3, $2, $1 0x x or $3, $2, $1 0x x nor $3, $2, $1 0x x slt $3, $2, $1 0x c 0x a 9 sll $3, $2, 1 0x x srl $3, $2, 1 0x x jr $2 0x c 0x nop 0x x

7 On Board Display and Control Setup INSTR=FFFFFFFF LCD Value = EEEEEEEE HEX7 HEX6 HEX5 HEX4 HEX4 HEX2 HEX1 HEX0 Toggle swiches Register, Instruction Memory or Data Memory Address Program Counter Clock Counter = Clock Control 0: manual clock 1: 1Hz clock 15,16 = LCD Value 00: Register 01: Data 10: Instruction SW[10-14] Instruction Memory Address SW[5-9] Data Memory Address SW[0-4] Register Address 0 Pushbutton Swiches Manual Clock RESET The project is reset by the push button 0 (KEY[0]). The program counter (HEX5 and HEX4) shows the instruction memory address. The clock counter (HEX0-4) shows how many cycles you design has run and it starts from 0. The LCD has two rows. The first row shows the instruction addressed by the program counter (HEX5 and HEX4). The second row shows the value which is controlled by SW[15-16], which could be a value pointed by a register address SW[0-4], or a data memory address SW[5-9] or a instruction memory address SW[10-14]. The actual address should be shown in HEX7 and HEX6. Your lab should be able to run by using two different clocks: (1) a system 1-Hz clock and (2) a manual clock. Use the switch SW[17] to switch between these two clocks. (If SW[17] = 0, the system 1Hz clock is used. Otherwise the manual clock is used.) Using the system clock allows your code to automatically complete the test programs. The manual clock is generated by the push button 1 (KEY[1]). For each push, generate a HIGH signal for only one second no matter how long the push button is pressed. Note that the LCD still needs the on-board clock. 7

8 Part 2: Show your Results on LCD and LED Each digit should stay on the LCD for a sufficient amount of time so that we can read it. For example, you could set the clock rate to 0.5Hz. Then every 2 seconds, an Ulam number is shown on the LCD. The numbers should be dynamically shown on the screen, i.e., you cannot just show all numbers together at the first step. Similarly your results should also be shown on the LED simultaneously. A sample Clock, LED LCD driver will be provided. The following shows some diagram of some drivers. LED Controller Push bottom Debounce LCD controller Clock Divider The LCD_Display is used to display static ASCII characters and changing hex values from hardware on a two-line LCD display panel. Number_Hex_Digits is used to set the size of the Hex_Display_Data input. Each hex digit displayed requires a 4-bit signal. The reset signal should be active high whenever you want update the LCD display. Make sure that the pins LCD_ON and LCD_BLON are set as active high. These two pins are not set by the controller. You can find more information about the LCD controller in the course project website. LCD_E is actually LCD_EN. The debounce circuit is used to filter mechanical contact bounce in the DE2 s push buttons. A shift register is used to filter out the switch contact bounce. The shift register takes several time spaced samples of the push button input and changes the output only after several sequential samples are the same value. Clock is a clock signal of approximately 100Hz that is used for the internal 50ms switch debounce filter design. The pb_debounced is the output. The output will remain Low until the pushbutton is released. 8