Seventies, Eighties, Nineties: The Seventies

Transcription

1 6.823, L4--1 Seventies, Eighties, Nineties: Convergence from Mainframes & Supercomputers to Microprocessors Asanovic Laboratory for Computer Science M.I.T. The Seventies Supercomputers (synonymous with Vector Machines) dominated the high-end scientific computing market Cray-1 CDC, Fujitsu, NEC, Hitachi 6.823, L4--2 Mainframes were thriving in enterprise computing IBM 370 and its clones, Burroughs, UNIVAC, DEC,... Minicomputers (cheaper versions of mainframes) created a large new market: departmental computing DEC PDP-11 & VAX Wang, Data General, Prime,... Microprocessors appeared, and first personal computers In 1971: Intel 4004 (4-bit, 750kHz) By 1979: Motorola (32-bit, 8MHz) Page 1

2 Seventies Technology 6.823, L4--3 Supercomputers and mainframes used mostly ECL - expensive - hot liquid cooling (plumbing!) - low density (SSI & MSI) chips - MTBF in days Minicomputers used mostly TTL technology - cheaper - air cooled - medium density (MSI & LSI) chips - very reliable, i.e., MTBF in weeks All machines except supercomputers used MOSFETs for memory chips Software in the Seventies 6.823, L4--4 Most programming was done in high-level languages Fortran, COBOL, Basic, Lisp, Pascal, Simula, C,... Time-sharing and interactive computing came into widespread use (screens versus punched cards) Most companies used proprietary Operating Systems IBM OS370, MVS,... DEC VMS,... Unix, a portable OS, was beginning to be used on minicomputers in universities Internet ( , FTP, TCP/IP,...) came into existence Page 2

3 Seventies General-Purpose Architectures 6.823, L4--5 (minicomputers and mainframes for business processing) Characteristics: Complex Instruction Sets: Microcoded Control Very Little Instruction Pipelining Caches Virtual Memory (IBM 360->370, DEC PDP-11->VAX) Sources of Complexity in ISAs Addressing modes Variable-length fields Macro-instructions - loop control - function call Regularity - most addressing mode for each operand - most operators for each data type 6.823, L4--6 Microprogramming made it possible to implement large and complex instruction sets at a reasonable cost Page 3

4 6.823, L4--7 VAX: A Complex Instruction Set Addressing Mode Syntax Length in bytes Literal #value 1 (6-bit signed value) Immediate #value 1 + immediate Register Rn 1 Register deferred (Rn) 1 Byte/word/long disp(rn) 1 + displacement displacement 1 + displacement displacement deferred Scaled (Indexed) base mode (Rx) 1 + base addressing mode Autoincrement (Rn)+ 1 Autodecrement -(Rn) 1 1 deferred ADDL3 R1, 737 (R2), #456 R1 <-- M[(R2)+737] ( ) + (1+ 4) = 10 bytes! Supercomputers 6.823, L4--8 Applications: Military research (nuclear weapons, cryptography) Scientific research Weather forecasting Oil exploration Industrial design (car crash simulation) 70s-80s, Supercomputer == Vector Machine Page 4

5 Vector Supercomputers 6.823, L4--9 (Epitomized by Cray-1, 1976) Scalar Unit + Vector Extensions Load/Store Architecture Vector Registers Vector Instructions Hardwired Control Highly Pipelined Functional Units Interleaved Memory System No Data Caches No Virtual Memory Vector Programming Model Scalar Registers Vector Registers r15 v , L4--10 r0 v0 [0] [1] [2] [VLRMAX-1] Vector Arithmetic Instructions VADD v3, v1, v2 v1 v2 v3 Vector Length Register VLR [0] [1] [VLR-1] Vector Load and Store Instructions VLD v1, r1, r2 v1 Vector Register Base, r1 Stride, r2 Memory Page 5

6 Vector Code Example 6.823, L4--11 # C code for (i=0; i<64; i++) C[i] = A[i] + B[i]; # Scalar Code li r4, #64 loop: ld f1, 0(r1) ld f2, 0(r2) fadd f3, f1, f2 st f3, 0(r3) add r1, r1, #1 add r2, r2, #1 add r3, r3, #1 sub r4, #1 bnez r4, loop # Vector Code li vlr, #64 lv v1, r1, #1 lv v2, r2, #1 faddv v3, v1, v2 sv v3, r3, #1 Vector Arithmetic Execution 6.823, L4--12 Use deep pipeline (=> fast clock) to execute element operations Simplifies control of deep pipeline because elements in vector are independent (=> no hazards!) V 1 V 2 V 3 Six stage multiply pipeline V3 <- v1 * v2 Page 6

7 Vector Memory System 6.823, L4--13 Cray-1, 16 banks, 4 cycle bank busy time, 12 cycle latency Bank busy time: Cycles between accesses to same bank Vector Registers Base Stride Address Generator A B C D E F Memory Banks 6.823, L4--14 Microprocessors in the Seventies Initial target was embedded control First micro, 4-bit 4004 from Intel, designed for a desktop printing calculator Constrained by what could fit on single chip Single accumulator architectures 8-bit micros used in hobbyist personal computers Micral, Altair, TRS-80, Apple-II Little impact on conventional computer market until VISICALC spreadsheet for Apple-II (6502, 1MHz) First killer business application for personal computers Page 7

8 First Microprocessor Intel 4004, , L bit accumulator architecture 8µm pmos 2,300 transistors 3 x 4 mm 2 750kHz clock 8-16 cycles/inst , L4--16 DRAM in the Seventies Dramatic progress in MOSFET memory technology 1970, Intel introduces first DRAM (1Kbit 1103) 1979, Fujitsu introduces 64Kbit DRAM => By mid-seventies, obvious that PCs would soon have > 64KBytes physical memory Page 8

9 Microprocessor Evolution 6.823, L4--17 Rapid progress in size and speed through 70s Fueled by advances in MOSFET technology and expanding markets Intel i432 Most ambitious seventies micro; started in released bit capability-based object-oriented architecture Instructions variable number of bits long Severe performance, complexity, and usability problems Intel 8086 (1978, 8MHz, 29,000 transistors) Stopgap 16-bit processor, architected in 10 weeks Extended accumulator architecture, assembly-compatible with bit addressing through segmented addressing scheme Motorola (1979, 8MHz, 68,000 transistors) First production microprocessor with microcode 32-bit general purpose register architecture (24 address pins) 8 address registers, 8 data registers Intel , L4--18 Class Register Purpose Data: AX,BX general purpose CX string and loop ops only DX mult/div and I/O only Address: SP stack pointer BP base pointer (can also use BX) SI,DI index registers Segment: CS code segment SS stack segment DS data segment ES extra segment Control: IP instruction pointer (lower 16 bit of PC) FLAGS C, Z, N, B, P, V and 3 control bits Typical format R (R) op M[X], many addressing modes Not a GPR organization! Page 9

10 The Eighties: Microprocessor Revolution Personal computer market emerges Huge business and consumer market for spreadsheets, word processing and games Based on inexpensive 8-bit and 16-bit micros: Zilog Z80, Mostek 6502, Intel 8088/86, 6.823, L4--19 Minicomputers replaced by workstations Distributed network computing and high-performance graphics for scientific and engineering applications (Sun, Apollo, HP, ) Based on powerful 32-bit microprocessors with virtual memory, caches, pipelined execution, hardware floating-point Massively Parallel Processors (MPPs) appear Use many cheap micros to approach supercomputer performance (Sequent, Intel, Parsytec) IBM PC, 1981 Hardware Team from IBM building PC prototypes in 1979 Motorola chosen initially, but was late IBM builds stopgap prototypes using 8088 boards from Display Writer word processor 8088 is 8-bit bus version of 8086 Estimated sales of 25,000 (100,000,000s sold) Software Microsoft negotiates to provide OS for IBM. Later buys and modifies QDOS from Seattle Computer Products. Open System Standard processor, Intel 8088 Standard interfaces Standard OS, MS-DOS IBM permits cloning and third-party software 6.823, L4--20 Page 10

11 Writable Control Store (WCS) Implement control store with RAM not ROM MOS memories now almost as fast as control store (core memories were 10x slower) Bug-free microprograms difficult to write 6.823, L4--21 WCS provided as option on several minicomputers Allowed users to change microcode for each process WCS failed Little or no programming tools support Hard to fit software into small space Microcode control tailored to original ISA, less useful for others Large WCS part of processor state - expensive context switches Protection difficult if user can change microcode Virtual memory required restartable microcode (Patchable microcode still common for post-fabrication bug fixes, e.g. Intel Pentium series) 6.823, L4--22 Reduced Instruction Set Computers (Cocke, IBM; Patterson, UC Berkeley; Hennessy, Stanford) Compilers have difficulty using complex instructions VAX: 60% of microcode for 20% of instructions, only responsible for 0.2% execution time IBM experiment retargets 370 compiler to use simple subset of ISA => Compiler generated faster code! Simple instruction sets don t need microcode Use fast memory near processor as cache, not microcode storage Design ISA for simple pipelined implementation Fixed length, fixed format instructions Load/store architecture with up to one memory access/instruction Few addressing modes, synthesize others with code sequence Register-register ALU operations Delayed branch Page 11

12 MIPS R2000 (One of first commercial RISCs, 1986) 6.823, L4--23 Load/Store architecture 32x32-bit GPR (R0 is wired), HI & LO SPR (for multiply/divide) 74 instructions Fixed instruction size (32 bits), only 3 formats PC-relative branches, register indirect jumps Only base+displacement addressing mode No condition bits, compares write GPRs, branches test GPRs Delayed loads and branches Five-stage instruction pipeline Fetch, Decode, Execute, Memory, Write Back CPI of 1 for register-to-register ALU instructions 8 MHz clock Tightly-coupled off-chip FP accelerator (R2010) RISC/CISC Comparisons 6.823, L4--24 Time = Instructions * Cycles * Time Program Program Instruction Cycle R2000 vs VAX 8700 [Bhandarkar and Clark, 91] R2000 has ~2.7x advantage with equivalent technology Intel vs Intel i860 (both 1989) Same company, same CAD tools, same process i x faster - even more on some floating-point tasks DEC nvax vs Alpha (both 1992) Same company, same CAD tools, same process Alpha 2-4x faster Page 12

13 VLIW (Very Long Instruction Word) 6.823, L4--25 Multiple parallel operations packed into single long instruction add r1, r2, r3 sub r5, r1, r3 ld r4, (r3) jmp #1499 FPS AP-120B, first commercial VLIW Scientific libraries coded by hand Fisher & Ellis, Yale, early 80s Proposed wide machines with simple control logic Develop compiler techniques to schedule parallel code Yale ideas commercialized by Multiflow (also Cydrome) Trace-28 executed 28 operations per cycle Trace-28 had 1024-bit instructions Intel i860 (1989) First dual issue microprocessor using 64-bit LIW (2 operations/inst.) The Nineties 6.823, L4--26 Distinction between workstation and PC disappears Parallel microprocessor-based SMPs take over lowend server and supercomputer market MPPs have limited success in supercomputing market High-end mainframes and vector supercomputers survive killer micro onslaught 64-bit addressing becomes essential at high-end In 2000, 4GB DRAM costs <$5,000 CISC ISA (x86) thrives! Page 13

14 6.823, L4--27 Reduced ISA Diversity in Nineties Few major companies in general-purpose market Intel x86 (CISC) IBM 390 (CISC) Sun SPARC, SGI MIPS, HP PA-RISC (all RISCs) IBM/Apple/Motorola introduce PowerPC (another RISC) Digital introduces Alpha (another RISC) Software costs make ISA change prohibitively expensive 64-bit addressing extensions added to RISC instruction sets Short vector multimedia extensions added to all ISAs, but without compiler support => Focus on microarchitecture (superscalar, out-of-order) CISC x86 thrives! RISCs (SPARC, MIPS, Alpha, PowerPC) fail to make significant inroads into desktop market, but important in server and technical computing markets RISC advantage shrinks with superscalar out-of-order execution Intel Pentium Pro (1995) 6.823, L4--28 External Bus L2 Cache Bus Interface Memory Reorder Buffer Data Cache x86 CISC macro instructions Instruction Cache and Fetch Unit Instruction Decoder Branch Target Buffer Micro- Instruction Sequencer Register Alias Table Reservation Station Memory Interface Unit Address Generation Unit Integer Unit Floating-Point Unit Reorder Buffer and Retirement Register File Internal RISC-like micro-ops Page 14

15 6.823, L4--29 Pentium Pro vs MIPS R10000 External Bus Interface Execution Units D-cache I-cache ISA Translation Execute target ISA binary on different host ISA Binary Translation (convert at install/load time) IBM AS/400 on PowerPC DEC VAX->MIPS->Alpha Emulation (interpret instructions at run time) Apple M68K emulation on PowerPC Dynamic Compilation (compile at run time) Sun s HotSpot Java JIT (just-in-time) compiler Transmeta Crusoe, x86->vliw code morphing Hardware Translation Intel Itanium (Merced) converts x86 to native VLIW format using hardware translator (Hardware supports two ISAs!) In future, might see further separation of software distribution format and hardware native ISA 6.823, L4--30 Page 15

16 6.823, L4--31 The Next Ten Years: Technology # transistors per chip 1M Million 2000 time Billion Silicon CMOS technology in 2010 will support: ~10 billion transistors per chip ~10 GHz clock rates Consider 1997 vintage 64-bit RISC processor: 4 way superscalar, outof-order, speculative execution with L1 I&D caches, L2 cache controller => ~6 Million Transistors What form will Giga-Transistor CPUs take? Even bigger caches (e.g., 100MB on-chip cache) Chip-scale multiprocessors (i.e., SMPs sans DRAM) Complete systems (i.e., CPU+DRAM+I/O) The Next Ten Years: Opportunities and Challenges 6.823, L4--32 Opportunities: 10 billion transistors/chip, 10 GHz clock rates ISA translation technology (remove ISA compatibility millstone) New applications and platforms (less reliance on legacy software)» The Post-PC era: ubiquitous, wireless, mobile, embedded, real-time» By 2010, we ll build 10 million transistors per person per day! Challenges: Power dissipation, both for high-end CPUs and portable devices Wire delay (10 cycles to move across chip!) Memory latency (1000 cycles to reach main memory!) Extracting parallelism from applications» hardware vs. compiler vs. programmer Processor design effort (i.e., can we manage/afford >1,000 engineer design teams?) Economics, new fabrication plant costs >$2 Billion and growing! Page 16