Design Tools for HPC SoC Challenges, Opportunities, or Business as Usual?
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1 Design Tools for HPC SoC Challenges, Opportunities, or Business as Usual? X. Sharon Hu Department of Science and Engineering University of Notre Dame
2 To SoC, or not to SoC If HPC does not adopt SoC design, what are the alternatives? If HPC adopts SoC design, should there be one or two or more SoCs? Cost vs. efficiency What IPs should go into the SoC(s)? Electronic Design Automation (EDA) Tools 2
3 SoC Design for Embedded Systems IP reuse, SoC design and integration started close to 3 years ago Myriad of tools available Commercial tools: Carbon Design Systems (Model Studio, SoC Design Plus, CPAK) Sonics (SonicsStudio Director) Synopsys (System Studio, Platform Architect) Cadence (System Development Suite) Open source or academic tools: Ptolemy II Baya (edautils) Verilator 3
4 ES SoC Design Methdologies Top-Down Design Platform-Based Design Functional Specification System function System Platform System Level Design Mapping Hardware Design Software Design Architectural Analysis/Refinement Co-Verification Integration Implementation 4
5 Metrics: quantifiable Design Space Exploration Performance (especially real-time) Energy Resiliency (lifetime, soft error tolerance, ) System-level design as multi-attribute optimization: Pareto-optimal solutions User-preference guided search 5
6 Design Space Exploration System-level design as multi-attribute optimization: Given design x i (i=1, N) with attributes a i (=1, M) Find the best design based on user s preference captured by an imprecise value function V w V Weight w i are implicitly constrained by user s preferences, i.e., if user prefers x i over x j, we have w ( V ( a ) V ( a )) Comparing alternative designs becomes min s. t. w ( V ( a w ( V ( a h i i ) V ( a ) V ( a i j )) )) j i for all i ( a i for all i and j ) 6
7 ES Design v.s. HPCS Design (1) Similarities Ever increasing hardware capability: multi-core, multithread, complex communication fabrics, memory hierarchy, Increasing productivity gap Common concerns: latency, throughput, energy, cost, reliability, fault tolerance, 7
8 ES Design v.s. HPCS Design (2) Differences (maybe) Application specific worloads v.s. domain specific worloads Miniapps can be a great asset for addressing this aspect More or less heterogeneity Constraints, objectives, desirables? Latency, throughput, energy, cost, reliability, fault tolerance, IP protection/privacy, T to M, Other issues: problem size, level of complexity, user expertise, Facing similar issues even today 8
9 Which Platform Is Better? i3+75 i7+75 i3+75 i7+75 i3+75 i STC SMA DA i3+75 i7+75 i3+75 i7+75 i3+75 i7+75 Time: sec Energy: joule STC SMA DA
10 Which Platform is Better? Unit: Joule*sec i3+75 i7+75 i3+75 i7+75 i3+75 i7+75 STC SMA DA 1
11 Time: sec Which Partition to Use? DP CP1 CP2 DP CP1 CP2 DP CP1 CP2 DP CP1 CP2 DP CP1 CP2 Energy: joule i3+75 i7+75 DP CP1 CP2 DP CP1 CP2 DP CP1 CP2 DP CP1 CP2 DP CP1 CP2 i3+75 i
12 What Runtime Strategy to Use? CG: speedup GHZ 2.6GHZ 3.2GHZ 3.5GHZ 3.8GHZ DA: speedup GHZ 2.6GHZ 3.2GHZ 3.5GHZ 3.8GHZ 12
13 Runtime Reliability-Aware Load Balancing Random Temperature-Aware Energy-Aware Reliability-Aware Normalized System MTTF Benchmar ~14-28% improvements 13
14 SoC Design Tools for HPC Modeling Multi-scale, multi-abstraction-level More sophisticated system SW models Simulation and analysis Miniapps Methods to aggregate results for different applications Memory and communication analysis and design Design space exploration Multiple-attribute optimization Runtime resource management Tradeoffs between cost and benefit 14
15 Than you! Comments? 15
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