Dependable VLSI Platform using Robust Fabrics
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1 Dependable VLSI Platform using Robust Fabrics Director H. Onodera, Kyoto Univ. Principal Researchers T. Onoye, Y. Mitsuyama, K. Kobayashi, H. Shimada, H. Kanbara, K. Wakabayasi
2 Background: Overall Design Technology Challenges (ITRS2011) Design productivity Power consumption Manufacturability Performance/power variability, device parameter variability, lithography limitations Interference Reliability and resilience Logic/circuit/physical: MTTF-aware design, builtin-self-repair, soft-error correction 1
3 Dependable VLSI Platform using Robust Fabrics Target: Resolving the challenges in Manufacturability, Variability, Aging, Soft errors, NRE-cost explosion Method: Collaborative researches for Layout/Circuit/Architecture/Mapping Layout: Robust structure for enhanced manufacturability Circuit:Adaptive performance tuning Architecture:Adaptive redundancy in reconfigurable architecture Mapping: dependability-aware HLS and mapping from C Goal: Dependability-aware VLSI Platform Reliability: Max Dependable Processor DMAC Reconfigurable Cluster Array (FRRARY) Reconfigurable Array I/F SRAM (Local Memory) WISHBONE External I/Fs Direct I/O Ext. I/O Application in C Digital Filter (FIR, IIR), CRC, FEC (LDPC,Viterbi), Cipher (AES), Reliability-aware Mapping (Controller, etc.) Mapping Reliability Reliability: Regular Area: Min. Area Reliability: High Area: Small Reliability Area Tradeoff Area-effective Mapping (Datapath etc.) Reliability & Area aware Mapping (I/Os, etc.) Reconfigurable Array Architecture using Robust Fabrics Dependable VLSI Platform 2
4 Research Team Robust Fabric Variation-tolerant fabrics Onodera, Sato, Tsuchiya (Kyoto U.) Reconfigurable Architecture Flexible reliability, hot swap Onoye, Hashimoto(Osaka U.), Mitsuyama (Kochi U. Tech.) Reliable Processor Reliability-aware circuit and architecture Kobayashi(KIT), Shimada, Yao(NAIST) Mapping Techniques Reliability-aware mapping Ochi, Tsutsui (Kyoto Univ.) C-language based Tool Reliability-aware HLS from C Wakabayashi, Takenaka, Noda(NEC) Applications Dependability measure, applications Kanbara (ASTEM) 3
5 Key Achievements Dependable Platform SoC 5 3 Dependable Processor DMAC SRAM (Local Memory) 4 Reconfigurable Cluster Array (FRRAry) Reconfigurable Array I/F Dependable VLSI Platform WISHBONE Ext. I/O Bus I/F Direct I/O Applications in C Digital Filter (FIR, IIR), CRC, FEC (LDPC,Viterbi), Cipher (AES), Mapping Reconfigurable Array Architecture using Robust Fabrics 1. Radiation tolerant flip-flop 2. Variability compensation by localized body biasing 3. Reliable pipeline processor 4. Reconfigurable architecture with flexible reliability 5. Dependable VLSI Platform SoC & C-based Design Tools 4
6 1. Radiation-tolerant FF: BCDMR FF # of errors in 50min. Neutron Irradiation for 202k BCDMR FFs well Clock Freq.[MHz] twin triple Conventional FF: #errors:260 Bi-stable Cross-coupled Dual Modular Redundancy FF Redundant FF for soft errors based on BISER(Intel, Stanford) Neutron irradiation test for 50min No error is observed in 202,000 BCDMR FFs (65nm) At least 260x stronger than conventional FFs Deliverable in 65nm 5
7 2. Variability Compensation by Localized Body Biasing Features Variability compensation by fine grained ( ~0.1mm 2 ) adaptive body biasing SS, SF, FS corner performance can be compensated to Typical Area overhead less than 3% Developed IPs All-digital pmos/nmos monitors Cell-base-designed body biasing circuits Other Features WID as well as D2D variability compensation Compatibility with Cell-base design Substrate island (SI) Built-in self-adjustment module (BISAM) Chip Localized Body biasing 6 6
8 3. Reliable Pipeline Processor : DARA DARA: Dynamic Adaptive Redundancy Architecture ==? ==? ==? ==? Next TMR building brick: pipeline DMR: address SEE TMR: locate defects DMR: salvage useful units α-particle stress test on a 180nm DARA chip 5x5mm 2, 180nm, 1.25V α-particle source HOST Test platform (chip under α-particle source) By scan-chain: 14.5 errors/60 sec in 1,080 unprotected FFs. Estimated SEE injection rate: 0.58 errors/sec Survived stress tests for 60s+. Not every SEE goes to error: 0.34 recoveris/sec in DARA
9 4. Reconfigurable Architecture with Flexible Reliability Coarse-grained reconfigurable architecture enabling adaptive redundancy and hot swapping Redundancy level can be selected for each processing element. minimize area and power overhead. Configuration memory can be protected by TMR. Target application domain can be expanded by adopting LUT-based fine-grained element. - 65nm CMOS - 4.2mm x 4.2mm - #clusters: - ALU : 26 - Memory: 6 - LUT : 80 DARA Memory clusters FRRARY LUT clusters ALU clusters Voter for config. mem Config. Mem Input from neighboring cluster Execution module Cell Execution module Cell Execution module Cell Execution module Cell Reconfigurable cell unit Redundancy ctrl unit Comp. and votin unit Selector Dependable VLSI platform SoC Output to neighboring cluster Cluster architecture 8
10 Combination of coarse-grained and fine-grained elements Control Datapath Application mapping Fine-grained element (LUT cluster) Dependable VLSI platform SoC Coarse-grained element 9 (ALU cluster)
11 5. Dependable VLSI Platform SoC and C-based Design Tools Dependable VLSI Platform Hardware Flexible Reliability Reconfigurable Array(FRRARY) Reliable Processor(DARA) Dependable VLSI Platform Software C-based High-Level Synthesis Reliability-aware Mapping Dependable VLSI platform Design Tools ANSI-C C-based HLS RTL Mapping DARA Memory clusters FRRARY LUT clusters ALU clusters DARA FRRARY FRRARY I/F WISHBONE Ext. I/O Controller Video I/O FRRARY Camera In SpW SRAM I/O FPGA Display Dependable VLSI Platform SoC Evaluation system 10
12 Dependable VLSI Platform using Robust Fabrics Target: Resolving the challenges in Manufacturability, Variability, Aging, Soft errors, NRE-cost explosion Solutions Fabrics: Radiation and variation tolerant FFs Circuit:Adaptive performance tuning by localized body biasing Architecture:Adaptive redundancy in reconfigurable architecture and processor Mapping: dependability-aware HLS and mapping from C Reliability: Max Goal: Dependable VLSI Platform Dependable Processor DMAC Reconfigurable Cluster Array (FRRARY) Reconfigurable Array I/F SRAM (Local Memory) Dependable VLSI Platform WISHBONE External I/Fs Direct I/O Ext. I/O Application in C Digital Filter (FIR, IIR), CRC, FEC (LDPC,Viterbi), Cipher (AES), Reliability-aware Mapping (Controller, etc.) Mapping Reliability Reliability: Regular Area: Min. Area Reliability: High Area: Small Reliability Area Tradeoff Area-effective Mapping (Datapath etc.) Reliability & Area aware Mapping (I/Os, etc.) Reconfigurable Array Architecture using Robust Fabrics 11
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