Computer Architecture

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1 Computer Architecture Pipelined and Parallel Processor Design Michael J. Flynn Stanford University Technische Universrtat Darmstadt FACHBEREICH INFORMATIK BIBLIOTHEK lnventar-nr.: Sachgebiete: Standort: Jones and Bartlett Publishers Sudbury, Massachusetts Boston London Singapore

2 Preface Acknowledgments xv xvii 1 Architecture and Machines Some Definitions and Terms Interpretation and Microprogramming The Instruction Set Basic Data Types Instructions Classes of Operations Instruction Mnemonics General Machine Conventions Branches Register Sets and Addressing Modes Instruction Code Examples Other Instruction Set Issues Program Size Addressing and Memory Process Addressing System Addresses and Segmentation ' Memory Space Virtual to Real Mapping Basic Instruction Timing Examples of Well-mapped Machine Instruction Timing Overlapped and Pipelined Processors Conclusions Historical Development of Computers Annotated Bibliography Problem Set 58

3 vi 2 Time, Area, and Instruction Sets Introduction Time The Nature of a Cycle Partitioning Instruction Execution into Cycles Clocking Overhead and Reliable Clocking Pipelined Processors Optimum Pipelining Cycle Quantization Wave Pipelining Cost-Area Area Data Storage Technology State of the Art The Economics of a Processor Project: A Study Phase 1: Development Phase 2: Early Manufacturing Phase 3: Production Phase 4: All Good Things Must Come to an End Instruction Sets: Processor Evaluation Metrics Program Execution Instruction Set Comparisons Invariant Effects Code Density Role of Registers, Evaluation Stacks, and Data Buffers Conclusions Some Areas for Further Research Data Notes J Annotated Bibliography Problem Set Data: How Programs Behave Introduction Instruction Usage Data Categories Format Distribution Operation Set Distribution Process Management Procedure Calls: User State Calls to the System 153

4 vii 3.4 Breaks in Machine Execution Instruction Run Length Branches Branch Target Distribution Condition Code Testing Move and Arithmetic Class Operations Register-Based Addressing Decimal and Character Operand Length Conclusions Some Areas for Further Research Data Notes Annotated Bibliography Problem Set Pipelined Processor Design Introduction Evolution of a Computer Processor Family Processor Design Organization of the Chapter Approaching Pipelined Processors Examples of Pipeline Implementations Evaluating Pipelined Processor Performance Design of a Pipelined Processor Cache Access Controller Accounting for the Effect of Buffers in a Pipelined System Buffer Design Designing a Buffer for a Mean Request Rate I-Buffers Designed for Maximum Request Rates Branches Branch Elimination Branch Speedup Branch Prediction Strategies Branch Target Capture: Branch Target Buffers Interlocks Decoder and Interlocks Bypassing Address Generation Interlocks Execution Interlocks and Interlock Tables Run-On Delay 250

5 viii 4.8 Miscellaneous Effects Store in Instruction Stream Delay Conclusions Some Areas for Further Research Data Notes Annotated Bibliography Problem Set Cache Memory Introduction Basic Notions Cache Organization Cache Data Adjusting the Data for Cache Organization Write Policies Strategies for line Replacement at Miss Time Fetching a Line Line Replacement Cache Environment Other Types of Cache Split I- and D-Caches I-and D-Caches Code Density Effects On-Chip Caches Two-Level Caches Logical Inclusion Write Assembly Cache Cache References per Instruction Instruction Traffic Data Traffic Technology-Dependent Cache Considerations Virtual-to-Real Translation Translation Lookaside Buffer (TLB) Overlapping the T cycle in V R Translation Set Associative Caches Virtual Caches Real Caches Using Colored Pages Studies Actual Reference Traffic Design Summary 336

6 ix Cache Evaluation Design Rules Cache/TLB Excess CPI Design Rules Conclusions Some Areas for Further Research Data Notes Bibliography Problem Set Memory System Design Introduction The Physical Memory The Memory Module Error Detection and Correction Memory Buffers Partitioning of the Address Space Models of Simple Processor-Memory Interaction Memory Systems Design Multiple Simple Processors Hellerman's Model Strecker's Model Rau's Model Processor-Memory Modeling Using Queueing Theory Performance Models of Processor Memory Interactions Arrival Distribution Service Distribution Terminology Queue Properties Open-, Closed-, and Mixed-Queue Models The Open-Queue (Flores) Memory Model Closed Queues Mixed Queues^ Waiting Time, Performance, and Buffer Size Pipelined Processors Designing a M/M/1 Buffer Given a Mean Queue Size Comparison of Memory Models Review and Selection of Queueing Models Processors with Cache Fully and Partially Blocking Caches Accessing a Line dime access) Contention Time d bu sy) ma Copyback Caches 400

7 6.8.4 I/O Effects Performance Effects Copyback Cache Study Simple Write-Through Caches Write-Through Cache Example Shared Bus Nonblocking Caches Interleaved Caches Conclusions Some Areas for Further Research Data Notes Annotated Bibliography Problem Set 420 Concurrent Processors Introduction Vector Processors Vector Functional Units Vector Instructions/Operations Vector Processor Implementation A Generic Vector Processor Vector Memory The Special Case of Vector Memory Modeling Vector Memory Performance Gamma (y)-binomial Model Bypassing between Vector Instructions Vector Processor Speedup Basic Issues Measures Multiple-Issue Machines Out-of-Order and Multiple-Instruction Execution Data Dependencies Representing Data Dependencies Other Types of Dependencies When and How to Detect Instruction Concurrency Two Scheduling Implementations An Improved Scoreboard Dealing with Out-of-Order Execution Interleaved Caches Branches and Speculative Execution 492

8 xi Adaptive Speculation Results Comparing Vector and Multiple-Issue Processors Cost Comparison Performance Comparison Alternative Organizations Conclusions Some Areas for Further Research Data Notes Annotated Bibliography.' Problem Set Shared Memory Multiprocessors Basic Issues Partitioning Scheduling Run-Time Scheduling Techniques Synchronization and Coherency The Effects of Partitioning and Scheduling Overhead Grain Size and Overhead Types of Shared Memory Multiprocessors Multithreaded or Shared Resource Multiprocessing Memory Coherence in Shared Memory Multiprocessors Shared-Bus Multiprocessors Snoopy Protocols Bus-Based Models Scalable Multiprocessors Directory-Based Protocols Directory Structure Invalidate Protocols Update Protocols Evaluating Some Systems Alternatives Interconnections Static Networks Links and Nodes Dynamic Networks Evaluating Interconnect Networks Direct Static vs. Indirect Dynamic Network Dimensionality and Link-Limited Network Hotspots and Combining 588

9 xii 8.18 Other Characterizations of Multiprocessors Conclusions Some Areas for Further Research Annotated Bibliography Problem Set I/O and the Storage Hierarchy The Role of I/O Evolution of I/O Systems Organization I/O Processors/Channels I/O System Support for Multiprocessors Design of Storage Systems Disk Technology The Disk Device Simple I/O Transactions Multiple Servers Single-Server Low Population (n) Disk Modeling Multiprogramming Models and Inverted Servers Improving I/O Response and Capacity I/O Traffic and Virtual Memory Effects Basic I/O Request Rate Virtual Memory I/O Traffic Disk Cache Buffers Concurrent Disks Clusters of Independent Disks Striping Disk Arrays Composite Configurations Some Practical Considerations Redundancy in Disk Arrays Conclusions Some Areas for Further Research Data Notes Annotated Bibliography Problem Set Processor Studies The Baseline Mark II Design Assumptions 664

10 xiii Design Alternatives Pipeline Timing Analysis Pipeline Penalty Analysis Cache and Memory Analysis Cost-Performance Analysis Area Performance Analysis of Processors The Problem Specifications Assumptions The Design Analysis Study Results Conclusions 718 Appendix A DTMR Cache Miss Rates 719 A.1 Basic DTMR 719 A.2 Associativity Adjustments 719 A3 User + System 721 A.4 Transaction-Based Systems 722 A.5 Multiprogrammed (Warm Cache) Environment 728 Appendix B SPECmark vs. DTMR Cache Performance 741 Appendix C Modeling System Effects in Caches 743 C.I Cold Start Cache 743 C.2 Cache Misses in Multiprogramming Environment 744 Appendix D New DRAM Technologies 747 D.I Typical Performance Enhancements 747 D.2 Enhanced DRAM 748 D.3 Synchronous DRAM 748 D.4 Cache DRAM 748 D.5 Rambus DRAM 748 D.6 RamlinkDRAM 749 D.7 Chip Level Summary 749 AppendixE M/G/l Queues 751 Appendix F Some Details on Bus-Based Protocols 755 Bibliography 765 Index 782

Computer Architecture A Quantitative Approach

Computer Architecture A Quantitative Approach Third Edition John L. Hennessy Stanford University David A. Patterson University of California at Berkeley With Contributions by David Goldberg Xerox Palo