Electronic Design Automation (EDA) Lab 電子設計自動化實驗室

Transcription

1 Electronic Design Automation (EDA) Lab 電子設計自動化實驗室 陳泰蓁 Tai-Chen Chen Department of Electrical Engineering National Central University Taoyuan 320, Taiwan 1

2 Education: Who am I? 1999/2001: B.S./M.S., Dept. of CS, Nat l Chiao Tung Univ., Taiwan 2007: Ph.D., Nat l Taiwan Univ. Join Next Technology Development Group, Springsoft Inc. after graduation Join Dept. of EE, Nat l Central Univ., Taiwan (2008/2) Research focuses: DFM-aware and PCB routing Electronic design automation (physical design) for analog and 3D ICs 2

3 2 Ph.D. students People at EDA Lab 李泰鋐, 黃保仁 (co-supervised with Prof. Chien-Nan Liu) 9 M.S. students 李培瑜, 葉欲名, 陳正傑, 賈立瑋, 王建騏, 劉宗祐, 王煜勛, 龐立遠, 劉家華 8 undergraduate project students 劉哲豪, 劉彥君, 李東原, 龍旻威, 張志銘, 郭玧質, 郭彥伯, 張耕瑋 3

4 alumni People at EDA Lab (Cont d) 洪牧新 ( 晨星科技 ), 張佳仁 ( 五年學碩士, co-supervised with Prof. Liu, 聯發科技 ), 管大宇 ( 新思科技 ), 賴弼廷 ( 凌陽電通 ), 王彥文 ( 澳洲 ), 蔡昀芷 ( 凌陽電通 ), 吳學謀 (co-supervised with Prof. Liu, 旺宏電子 ), 李家儀 ( 新思科技 ), 林昶甫 ( 新思科技 ), 張奕淳 ( 工研院 ), 謝崇暉 ( 服役 ), 蔡獻霆 ( 五年學碩士, 群聯電子 ), 劉國鼎 (), 陳進曜 ( 服役 ), 葉仲維 (), 黃俊霖 (nvidia) 陳國隆, 李佳憲, 何孟宣, 林晉宇, 洪源懋, 康明凱, 葉仲維, 葉欲名, 賈立瑋, 謝詩安, 謝弘毅, 林國裕, 韓承佑, 龐立遠, 陳泰宇, 程平洋, 郭明軒, 鄭宇辰, 黃資佑, 黃蛟晟, 侯柏帆, 王偉政, 劉凱瑞, 李冠德 4

5 EDA: Where Electronics Begins!!! Electronic Design Automation: Use software to design electronic devices/chips and their design services. 5

6 IC Design Flow 6

7 Physical Design Physical design converts a circuit description into a geometric description. The description is used to manufacture a chip. physical design fabrication 7

8 Physical Design Flow B*-tree based floorplanning system A routing system 8

9 Pentium 4 Floorplan Examples PowerPC 604 Intel Pentium 4 A floorplan with interconnections 9

10 Placement Examples 10

11 Routing Example Circuit: RISC1 from Faraday Die size: x um 2 #Nets: 34k Routing result Congestion map 11

12 Nanometer Design Challenges Feature Size 65 nm Frequency 5 GHz Die Size 600 mm 2 Transistor Count Per Chip 500 M Supply Voltage 0.9 V Wiring Level 9 Layers Power Consumption 170 Feature size : sub-wavelength lithography (impacts of process variation)? noise? reliability? Frequency, dimension : interconnect delay? electromagnetic field effects? timing closure? Chip complexity : large-scale system design methodology? SoC technology? Supply voltage : signal integrity (noise, IR drop, etc.)? Wiring level : manufacturability? 3D layout? Power consumption/density : power & thermal issues? 12

13 Design Complexity Increases Dramatically!! PowerPC 604 Intel Pentium 4 13

14 Interconnect Dominates Circuit Performance!! Interconnect Problem Source: Cadence Design System For 90 nm technology, interconnect delay dominates 75% of the overall delay. 14

15 Power/Thermal Is Another Big Problem!! Power density increases exponentially! Fred Pollack, New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies, 1999 Micro32 Conference keynote. Courtesy Avi Mendelson, Intel. 15

16 Subwavelength Lithography Causes Problems!! Mask patterns Printed image 16

17 3D ICs (Stacking) Bring New Design Issues!! Use via-first TSV process and face-to-back die stacking 17

18 Analog Design Is Becoming More Automated!! 18

19 The EDA Job Market Students working in this area typically had no problem getting jobs EDA-Related Careers in Taiwan Research Institute Foundry EDA Design Service IC Design House Academia Sinica ITRI TSMC UMC Apache DA Cadence Mentor Graphics Synopsys Faraday Global Unichip Goya Socle Verisilicon Broadcom Himax MediaTek Novatek Realtek Sunplus VIA 19

20 Students Wanted! Who are interested in problem solving Graduate: Master/Ph.D. ( 碩博研究生 ) Undergraduate: Sophomore/Junior/Senior ( 大二 ( 含 ) 以上專題生 ) Contact: 陳泰蓁 Tai-Chen Chen tcchen@ee.ncu.edu.tw Office: E1-324, (03) ext 李泰鋐 / 葉欲名 / 陳正傑 / 賈立瑋 / 王建騏 Lab: E1-359, (03) ext

21 邏輯設計 Requirements 動機 English EDA 高 EQ/ Integrity 程式實作資料結構演算法 基礎電路學 21