System-on-Chip (SOC) 晶 系統組

Transcription

1 專題 學程說明會 System-on-Chip (SOC) 晶 系統組 葉經緯 王進賢 朱元三 蔡宗亨 崇勛 林柏宏

2 What s hot in your life?

3 More Deeply! Information Navigation Social Activity Translation Face Recognition - Searching

4 SoC Applications Consumer Electronics Bioelectronics Automotive Electronics Wireless Sensor Network

5 How to realize?

6 SoC Architecture Power Regulator

7 Taiwan SoC/Semiconductor Industry

8 SoC-Related Research Fields System design ¾ FPGA prototyping ¾ 葉經緯教授 朱元三教授 黃崇勛教授 林柏宏教授 Circuit design ¾ Analog, digital, memory, power regulator, MEMS, ¾ 王進賢教授 蔡宗亨教授 黃崇勛教授 Computer-aided design or EDA ¾ Design automation, synthesis, simulation, verification ¾ 林柏宏教授

9 System Design System prototype on FPGA Term Project PART A csc Input TP Peripheral Part rst_n BCHS Scaling Engine Power On Reset VDD host_reg_a host_reg_b csc I2C Dither Gamma srgb TP Arbiter DRAM Controller System PLL PWM PART B SDRAM MHz LB ADC 1MHz 8051 SPI ROM OD SPI controller host_reg_sys Visual Flow Initial Setting Setting Log GUI setting windows

10 Circuit Design Paper study for specific circuitry ¾ Memory, ADC/DAC, Regulator.and so on Reference

11 SoC Design Challenges In 2007, feature size» 65 nm, µp frequency» 5 GHz, die size» 600 mm 2, µp transistor count per chip» 500M, wiring level» 9 layers, supply voltage» 0.9 V, power consumption» 170 W. ¾ ¾ ¾ ¾ ¾ Chip complexity n Effective design and verification methodology? More efficient optimization algorithms? Time-to-market? Power consumption n Power & thermal issues? Supply voltage n Signal integrity (noise, IR drop, etc)? Feature size, dimension n Sub-wavelength lithography (impacts of process variation)? noise? wire coupling? reliability? manufacturability? 3D layout? Frequency n Interconnect delay? electromagnetic field effects? timing closure? 11

12 Computer-Aided Design (CAD) Design Flow Coding Styles Lint (SpringSoft) Leda (Synopsys) Design Implementation -- RTL Design Entry VHDL Verilog Design Verification -- RTL Test Bench VHDL Verilog Design Verification Gate Level Post Layout Design Entry Gate Level Netlist -- HDL Code Technology Library Synthesis Design Compiler (Synopsys) Ambit (Cadence) Scan Synthesis DFT Compiler (Synopsys) Turbo Scan (Syntest) DFT - Fast Scan (Mentor) Simulation Verilog-XL (Cadence) NC-Verilog (Cadence) VCS (Synopsys) ModelSim (Mentor) Debugging Verdi (SpringSoft) Code Coverage Verification Navigator (TransEDA) RTL Power Analysis PrimePower (Synopsys) Formal Verification LEC (Cadence) Formality (Synopsys) Place and Route Clock Tree Insertion SOC Encounter (Cadence) Astro (Synopsys) Gate Level Netlist (After APR) Design Entry Phantom Layout (After APR) Design Verification Gate LevelDesign Entry Formal Verification LEC (Cadence) Formality (Synopsys) Gate Level Design Netlist Entry -- HDL Code Gate Level Netlist -- HDL Code Timing Verification PrimeTime (Synopsys) Power Optimization Power Compiler (Synopsys) Timing Verification PrimeTime (Synopsys) Gate Power Analysis RC Extraction XCalibre (Cadence) Star-RCXT (Synopsys) Calibre (Mentor Graphic) Layout Merge SOC Encounter (Cadence) Astro (Synopsys) Design Entry Design Entry Hard Macro Layout Design Entry Golden RTL Place and Route SOC Encounter (Cadence) Astro (Synopsys) Gate Simulation Verilog-XL (Cadence) NC-Verilog (Cadence) VCS (Synopsys) ModelSim (Mentor) Gate Power Analysis Design Entry Gate Level Netlist (Power Optimized) PrimePower (Synopsys) Gate Post Simulation Verilog-XL (Cadence) NC-Verilog (Cadence) VCS (Synopsys) ModelSim (Mentor) Layout PrimePower (Synopsys)

13 SOC 學程科目 ( 大一 ~ 大四 ) 大一上微積分 ( 一 ) 邏輯設計邏輯設計實驗計算機概論普通物理 ( 一 ) 大一下 微積分 ( 二 ) 線性代數 程式設計 程式設計實習 普通物理 ( 二 ) 大二上 微分方程 電子學 ( 一 ) 電路學 ( 一 ) 資料結構 數位系統設計 FPGA 數位設計實驗 需同時選修 大二下 機率 電子學 ( 二 ) 訊號與系統電磁學 ( 一 ) 計算機組織 三科選一 大三上 類比積體電路設計導論 作業系統導論 演算法導論 嵌入式系統 超大型積體電路設計導論 大三下 超大型積體電路專題 ( 一 ) IC 設計實驗 硬體描述語言程式設計與模擬 計算機結構 需同時修習 二科選一 大四上 ( 研究所 ) 超大型積體電路專題 ( 二 ) 數位矽智產設計 奈米積體電路設計 特殊應用積體電路設計 類比積體電路設計 射頻通訊積體電路設計 通訊積體電路設計 超大型積體電路設計自動化 SOC 設計方法論

14 SOC 學程選修 ( 大四 ~ 研究所 ) 教授大四 研上大四 研下 葉經緯數位矽智產設計 王進賢奈米積體電路設計 朱元三 SOC 架講設計 SOC 設計方法論 嵌入式記憶體設計 蔡宗亨通訊積體電路設計 混合訊號積體電路設計 黃崇勛低功率積體電路設計 特殊應用積體電路設計 林柏宏奈米積體電路實體設計超大型積體電路設計自動化