Cell-Based Design Flow

Transcription

1 Cell-Based Design Flow Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan

2 Outline Introduction Topics Verilog and Simulation Design Compiler SOC Encounter 2

3 40nm 16-core SPARC SoC Processor Source: J. L. Shin, et al., JSSC Major components 1. Digital circuit 2. Memory circuit 3. Analog and mixed-signal (AMS) circuit Design-for-testability features: 1. Scan test + test compression 2. Memory built-in self-test (MBIST) + repair 3. SerDes internal and external look-back tests 3

4 A Digital Circuit Source: T. Kurafuji, et al., JSSC Design Entry: Hardware description language (HDL) 1. Verilog 2. VHDL 4

5 A Memory Circuit Memory Cell Address Row Decoder Column decoder Data I/Os Source: K. Zhang, et al., ISSCC

6 VLSI Realization Process Customer s need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer 6

7 Definitions Design synthesis Given an I/O function, develop a procedure to manufacture a device using known materials and processes Verification Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function Test A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect 7

8 VLSI Design Cycle Concept Design Validation Designer Behavior Specification Final Product Manufacturing Product Verification RTL Verification Behavior Synthesis RTL Design Layout (Masks) Layout Synthesis Layout Verification Logic Verification Logic Synthesis Netlist (Logic Gates) 8

9 Verification The four representations of the design Behavioral, RTL, gate level, and layout In mapping the design from one phase to another, it is likely that some errors are produced Caused by the CAD tools or human mishandling of the tools Usually, simulation is used for verification, although more recently, formal verification has been gaining in importance Two types of simulations are used to verify the design Functional simulation & timing simulation 9

10 Functional & Timing Simulations Functional simulation No delays (or, at most, constant delay) of the functional units are included The primary concerns To check if each block performs intended function To modify the design to evaluate alternatives before finalizing the design Timing simulation The delays associated with the various gates are assigned Usually, nominal delays are assigned to the gates Actual verification of the prototype gives more assurance, since it embodies the process-dependent parameters 10

11 What is Synthesis Synthesis = translation + optimization + mapping if(high_bits == 2 b10)begin residue = state_table[i]; end else begin residue = 16 h0000; end HDL Source (RTL) Translate (HDL Compiler) No Timing Info. Generic Boolean (GTECT) Optimize + Mapping (HDL Compiler) Timing Info. The synthesis is constraint driven and technology independent!! Target Technology

12 Course Objective What can you learn from this course? Verilog RTL coding techniques SRAM memory complier Tools of cell-based design flow Once you get the credit of this course, you can design a digital circuit with SRAMs 12

13 Verilog module toll_booth(clk,rst,car_in,change_ok,green); input clk,rst,car_in,change_ok; output green; reg[1:0] state_reg, next_state; parameter IDLE = 2 b00; parameter WAIT = 2 b01; parameter EXIT = 2 b11; clk or posedge rst) begin If (rst==1 b1) state_reg<=idle; else state_reg<=next_state; end or car_in or change_ok) begin case(state_reg): IDLE: if (car_in==1 1) begin next_state=wait; green=1 b0; end else begin next_state=idel; end WAIT: if (change==1 b1) begin next_state=exit; green=1 b1; end else begin next_state=wait; green=1 b0; end EXIT: if (car_in==1 1) begin next_state=exit; green=1 b1; end else begin next_state=idel; green=1 b0; end default: begin next_state=idle; green=1 b0; end endcase end endmodule Input (car_in, change_ok) state_reg rst clk Combinational Logic state next_state output (green) 13

14 Memory Compiler Artisan SRAM Types: Generator Product Name Executable High-Speed/Density Single-Port SRAM SRAM-SP ra1sh High-Speed/Density Dual-Port SRAM SRAM-DP ra2sh High-Density Single-Port SRAM SRAM-SP-HD ra1shd High-Density Dual-Port SRAM SRAM-DP-HD ra2shd Low-Power Single-Port SRAM SRAM-SP-LP ra1shl [REF: Artisan User Manual] Only ra1shd and ra2sh are supported in school Generated files: Memory Spec. (i.e. used for layout-replacement procedure in CIC flow) Memory Data Sheet Simulation models: Verilog Model & VHDL Model Memory Libraries for P&R: Synopsys Model & VCLEF Footprint Timing Files: TLF Model & PrimeTime Model

15 Single-Port SRAM CLK WEN[*] CEN OEN A[m-1:0] D[n-1:0] SRAM Q[n-1:0] Name Type Description CLK Input Clock Basic Pins WEN[*] Input Write enable, active low. *If word-write mask is enabled, this becomes a bus CEN Input Chip enable, active low OEN Input Tri-state output enable A[m-1:0] Input Address (A[0]=LSB) D[n-1:0] Input Data inputs (D[0]=LSB) Q[n-1:0] Output Data outputs (Q[0]=LSB)

16 Waveforms for Single-Port SRAM Read Cycle t cyc t cyc t ckh t ckl t ckh t ckl CLK t cs t ch t cs t ch t cs t ch CEN t ws t wh t ws t wh WEN 1 t as t ah t as t ah A[ j ] ADD1 ADD2 Q[ i ] t a Q1 t a Q2

17 Cell-Based Design Flow Spec. System Level MATLAB/ C/ C++/ System C/ ADS/ Covergen (MaxSim) Memory Generator RTL Level Verilog/ VHDL NC-Verilog/ ModelSim Debussy (Verdi)/ VCS Syntest Logic Synthesis Design for Test Gate Level Layout Level Post-Layout Verification Conformal/ Formality Design/ Power Compiler DFT Compiler/ TetraMAX NC-Verilog/ ModelSim Debussy (Verdi)/ VCS SOC Encounter GDS II DRC/ LVS (Calibre) Physical Compiler/ Magma Blast Fusion PVS: Calibre xrc/ NanoSim (Time/ Power Mill) Tape Out

18 Course Schedule and Grading 日期課程內容主要負責人 10 11/13-11/19 硬體描述語言 1. 硬體描述語言語法教學吳冠德 11 11/20-11/26 硬體描述語言 1. 硬體描述語言編碼格式教學吳冠德 12 11/27-12/3 硬體描述語言 LAB 實作吳冠德 13 12/4-12/10 電路硬體合成 1. 硬體電路操作行為解說周哲緯 14 12/11-12/17 電路硬體合成 1. 電路硬體合成指令與流程教學 2.LAB 實作 周哲緯 15 12/18-12/24 電路硬體擺放與繞線 1. 電路擺放概念與設定檔案介紹侯致聖 16 12/25-12/31 電路硬體擺放與繞線 1. 電路擺放與繞線流程介紹 2. LAB 實作 侯致聖 17 1/1-1/7 電路硬體擺放與繞線 1.LAB 實作侯致聖 18 1/8-1/14 期末考周 1. 電路硬體合成 2. 電路硬體擺放與繞線 Grading 1. Lab 30% 2. Exam 20%