Automatic Post Silicon Clock Scheduling 08/12/2008. UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering

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1 UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Computer Architecture ECE 568 Power Issues in Computer Architecture Fall 2008 Power Density Trend for Intel mp 1000 Watt/cm i386 i486 Pentium Pentium Pro Pentium II Pentium III Pentium IV Nuclear Reactor Pollack, Fred. New Microarchitecture Challenges in the Coming Generations 2 of CMOS Process Technologies, MICRO-32 Keynote Talk, Nov

Fried Egg - Athlon XP1500+ Source: The New York Times, 25 June 2002 3 Battery (hand-held) Predictions Hand-held W 3.5 3 2.5 2 1.5 1 0.

2 Fried Egg - Athlon XP1500+ Source: The New York Times, 25 June Battery (hand-held) Predictions Hand-held W International Roadmap for Semiconductors: High-Performance Year Cost Mid-Performance W Year Year International Roadmap for Semiconductors, 2003 Edition, 4

Cost of High Power For high-end: Constantly increasing number of computers used, and the power that each consumes Electricity is expensive: financially and environmentally For mobile: Battery power

3 Cost of High Power For high-end: Constantly increasing number of computers used, and the power that each consumes Electricity is expensive: financially and environmentally For mobile: Battery power cannot keep up with processor power K. Lahiri, et al., Battery driven system design: a new frontier in low power design, in Proc. ASP-DAC/Int. Conf. VLSI Design, pp , Jan Electricity Usage Total power consumption of CPUs in PCs: 1992: 160Mwatts (87M CPUs) 2001: 9000Mwatts (500M CPUs) Data center: sq ft., ~8000 servers: 2Mwatts Source: Dataquest 6

4 High power fi Increasing Temperature With increased temperature: Current (& thus speed) decreases exponentially Diodes: I = I s (e V/nVt 1), Vt = kt/q, T=temperature Resistors: R T, I = V/R Rule of thumb: Speed 0.15% per 1 C But leakage current increases with temperature Thermal runaway temp leakage self-heating temp Reliability decreases exponentially T C Chip lifetime 50% 7 CPU Power Breakdown Fetch 6% Exec 22% Mem 26% Issue 46% Data Flow 11% I/O 7% PLA ROM 5% 2% Control L. 16% TLB 17% Clock 19% Cache 23% EBOX 8% Clock 10% DMMU 8% IMMU 9% Others 5% Dcache 16% Icache 26% Ibox 18% Alpha Power PC Strong ARM Alpha PowerPC StrongARM Relative consumption of processor units varies by application Approaches to reducing power must also vary 8

5 Power Reduction: Current Approaches Voltage Scaling Clock Throttling/Gating Fetch Throttling Energy vs. Power Decreasing power does not always P = mean decreasing energy If power decrease can make process take more time, it may take more energy Power constrained vs. Energy constrained e.g., Solar vs. Batteries de dt 9 CMOS Power Power consumption can be categorized: Consumed during switching - dynamic Consumed constantly - static Dynamic + Short Circuit Static J. A. Butts and G. S. Sohi. A static power model for architects. In Micro-33, pages , Dec

6 Dynamic Power PDYNAMIC = CL NSW C L = load capacitance = avg switches/cycle N SW V 2 DD f Currently largest portion of consumption Reducing N SW : Gating Throttling Short circuit power <10% of dynamic power Consumed briefly when PMOS and NMOS are on simultaneously 11 Static (leakage) power Constant Leakage through NMOS when logic result is high Importance increasing as technology size decreases One solution: disable portions of µp when not needed Kim, Nam Sung. Circuit and Microarchitectural Techniques for Processor On-Chip Cache Leakage Power Reduction. Thesis, Univ. of Michigan, pdf 12

7 Local Clock Gating Disable clock to inactive units Can disable global clock if stalled Can disable local clocks when particular functional units are not in use e.g.: may not have any multiply operations for unit to process Al-Khairi, S. Power Management Features On The Embedded Ultra Low-Power Intel486 Processor 13 Example of Throttling Fetch Unit can watch branch decisions in pipeline and stop putting instructions into pipeline If fetch unit is throttled no power is consumed Speculative branches cause 16% to 105% instruction overhead If fewer incorrect branches are fetched, can reduce power significantly with minor performance cost Calculate a confidence level Don t fetch uncertain branches Alternatively: slow fetch relative to the number of instructions committed 14

8 Dynamic Power Reduction through Voltage Scaling P = C N V 2 DYNAMIC L SW DD δ=delay; α, K are process-dependent 1<α<2 V DD δ δ f Decreasing V DD results in reducing average dynamic power cubically Since time to complete increases, energy consumed is reduced only by square f δ C = K V L DD ( VDD vt ) α 15 Dynamic Voltage Scaling (DVS) Run-time algorithms Design processor for maximum performance When maximum performance is not required, scale frequency and supply voltage appropriately DVS in Modern µp: Speedstep (Pentium IIIM, CeleronM, IV) Controlled by operating system Intelligent Energy Management (ARM µps) Processes submit performance requests to this software The software decides what requests to honor, directs hardware Genossar, D.; and Shamir. N. Intel Pentium M Processor Power Estimation, Budgeting, Optimization, and Validation. Intel Technology Journal. (May 2003). Flautner, K., et al A Combined Hardware-Software Approach for Low-Power SoCs DesignCon

Power Issues in Multi-Many Core 17 Why Multi-Core? Single Core Performance is unable to keep pace with the increasing transistor counts. Law of diminishing returns prevailing.

9 Power Issues in Multi-Many Core 17 Why Multi-Core? Single Core Performance is unable to keep pace with the increasing transistor counts. Law of diminishing returns prevailing. Power usage and heat generation increasing Multi-Core Performance is increasing as the multi-cores can utilize Thread level parallelism More power efficiency lower die temperature Improves reliability and leakage Based on Intel tests using the SPECint2000 and SPECfp2000 benchmarks 18

10 19 Dual Core Prof Koren 20

11 Cache Coherence Since one or more levels of private cache How to keep consistency across all the cores? 21 Cache Coherence problem Core 1 Core 2 Core 3 Core 4 One or more levels of cache x=15213 X=21660 One or more levels of cache X=15213 One or more levels of cache One or more levels of cache Main memory x=15213 Core 1 2 changes 1 reads x multi-core chip 22

12 Solutions to Cache Coherence Problem Invalidation Protocol with Snooping Invalidation : If a core writes a data item, it sends invalidation requests Snooping : All other cores snoop the data Validation Protocol Broadcasts updated value What happens when the number of cores increase? 23 Multi-Threading is the key in multi-core Threads are a way for a program to fork (or split) itself into two or more simultaneously running tasks. Several Threads CORE 1 CORE 2 CORE 3 CORE 4 24

13 Power 1K Cores on a Die At the least 1W per core 1K Watts of power Power efficiency is very critical in many-core architecture Shekar Borkar, Intel 25 From Multi to Many-Cores By Billion Transistors on a 300mm 2 The question is Less number of cores with more area OR More number of cores lesser area What Should be the tradeoff? Anant Agarwal et al 26

14 KILL Rule 1% Increase in core area should result in at least 1% increase in core performance Anant Agarwal et al 27 Kill Rule Example : MPEG2 Decode Assumption 512 byte occupies 1% of the core area IPC is used as the performance metric One third instruction are load and store instructions Core IPC= 1/(1+0.33xmx300) = 1/(1+mx100) where m is the data cache miss rate m For mpeg2 decode with 512 byte cache, m=0.25 Core IPC = 0.04 For 100 cores the IPC = 4 If the data cache increases to 2K bytes, m=0.05 So new IPC for the entire chip = 17 So Area 3% increase, performance increased by 325% Anant Agarwal et al 28

15 Kill Rule 3% increase 4% GOOD 325% increase 14% 47% 24% 7% 3% Anant Agarwal et al 29 In simple what does Kill Rule say? Can t follow existing single processor design approach Increase cache size Increase pipeline stages Many Port Register files Simpler Core and Smaller caches Can t keep on increasing the number of cores without striking the right balance Power Efficiency and performance Anant Agarwal et al 30

16 Kill Rule for Power Whetstone Area Increase=25% 0.03 Area Increase=4% IPC/Watt Increase=27% Area Increase=8% IPC/Watt Increase=13% Area Increase=14% IPC/Watt Increase= -6% IPC/Watt Increase= -6% IPC/Watts No. of cores 31 Performance of Many-Core Systems Amdahl s law Parallel Speedup is limited by serial code in a program Multi-Thread is vital. Shekar Borkar, Intel 32

Fine Grain Power Managment Leakage power contributes to 40% of the total power in the microprocessors Voltage Scaling -- Intel Frequency Scaling Multiple Vt Body Biasing Design style changes Avoid

17 Fine Grain Power Managment Leakage power contributes to 40% of the total power in the microprocessors Voltage Scaling -- Intel Frequency Scaling Multiple Vt Body Biasing Design style changes Avoid Domino logic Power Consumption for 300mm 2 after power management will be approximately 300W Shekar Borkar, Intel 33 Nothing is free Latency 1 Microseconds sleep latency, 2 clock cycles wake up latency for a single microprocessor. sleep transistor technique can reduce leakage by 37% at a 3% 4% performance reduction -- Intel Asynchronous Interfaces Different cores running at different frequency and voltages 34

18 On-Chip Network Power Networks are power hungry Eg: 500mW of power at each node More number or cores, More number of nodes, So More power. 35 Memory 100 s of GB of memory bandwidth is required Memory bus consumes around 25W for 100GB/s memory bandwidth Need to reduce the bus lengths 3D integration of memory with processor is a potential solution Shekar Borkar, Intel 36

2 32 KBdata caches (D$), 2 floating point unit for 4 cores So resource sharing, low power and area without affecting performance But need to find

19 SPARC Processor -- ROCK 16 Core, 14mm 2 32 Thread 32 Scout Thread 2.3 GHz, 396mm 2, 65nm Each core ~10W power No re-order buffer Out of order commit No crossbar network Cluster of 4 cores, each shares an I$ 32 Kb, 2 32 KBdata caches (D$), 2 floating point unit for 4 cores So resource sharing, low power and area without affecting performance But need to find it 37 ROCK SPARC Processor 16 Core 4 clusters, 4 cores each 2.3 GHz, 65nm 396 mm 2 Scout Thread 2 integer execution unit/core 2 FPU/cluster 32KB I$ and two 32KB D$ /cluster Power 250 W Marc Tremblay et al, SUN Microsystems 38

20 Main Highlight : Scout Threading Scout Thread Prefetches code and data Predicts and resolves branches Retires instructions which are not dependent on the outcome of the stuck instruction In simple out of order execution and out of order committing resulting in higher performance and throughput Avoids power hungry CAM based Re-Order Buffers Deferred queue 128 entry Low power SRAM High Single thread performance 39 How does ROCK compare to Niagara ROCK 240 W 16 Cores 2 Integer execution units/core 2 floating point unit /4 core 396 mm 2 2 threads/core Scout threads No Reorder buffer 2 levels of cache sharing Transactional Memory 2.4GHz Niagara 123 W 8 Cores 2 Integer execution units/core 1 floating point unit/core 342 mm 2 8 threads/core No scout threads Has Reorder Buffer 1 level of cache sharing Lock based synchronization 1.4GHz 40

Advanced Processor Architecture. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

Advanced Processor Architecture Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Modern Microprocessors More than just GHz CPU Clock Speed SPECint2000