A new Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FDSOI based on Cadence VP6 Technology
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1 Dr.-Ing Jens Benndorf (DCT) Gregor Schewior (DCT) A new Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FDSOI based on Cadence VP6 Technology Tensilica Day th Feb. 2017, Leibniz University Hanover, Germany
2 DCT Company Profile Dream Chip Technologies Positioned as a Fabless Microelectronic Engineering Company for medium to large SoC designs covering the whole range from Architecture, Specification, Design, Verification to GDSII Technologies: 130nm, 40nm, 28nm, 22nm FDX, 14/16nm FF 60 Employees/ 52 Engineers with years SoC design experience Based in Hanover (HQ) and Hamburg, Germany Member of Silicon Saxony/ Germany! Cadence Design Center Partner for Tensilica Dream Chip Technologies Confidential 2
3 Assisted Driving requires Cameras, Radar and Ultrasonic Dream Chip Technologies GmbH Dream Chip Technologies Confidential Source: Texas Instruments
4 Use Case #1: Digital Mirroring Dream Chip Technologies Confidential 4
5 Use Case #1: Digital Mirroring - The Multiview Automotive multi camera systems for Bird-View, Rear-View and Panorama-View are a major part of today s emerging technologies to make driving more safe and comfortable and to move towards autonomous vehicles. Dream Chip Technologies Confidential 5
6 Use Case #2 : 360 deg Top View Camera Dream Chip Technologies Confidential 6
7 Use Case #3 : Pedestrian detection via CNNs Dream Chip Technologies Confidential 7
8 Dream Chip Technologies Confidential Dream Chip Technologies GmbH
9 Introduction Image Sensor Processing Overview Dream Chip Technologies Confidential 9
10 Heterogeneous Cores for Image Sensor Processing CPU GPU (VP) DSP (VP, CPU) Vector DSP (VP, HW) Dream Chip Technologies Confidential 10
11 Example: 360 deg Top View Tasks: Fish-Eye Lens correction, Stitching, Warping, Photometric synchronization for ADAS surround sensors Mapping: HDMIin, HD-SDI HDMIout Dream Chip Technologies Confidential 11
12 Dream Chip Technologies Confidential Dream Chip Technologies GmbH
13 Low Power CNN Architecture Proposal Dream Chip Technologies GmbH Lock-Step ARM A53: Object L. VP6: Pixel Level HEs: Pixel Level I/O IF Memory IF Dream Chip Technologies Confidential 13
14 Vision P6 architecture VLIW & SIMD ALU Ops Memory width # of vector registers 32 5 issue slots 64way 8-bit 32way 16-bit 16way 32-bit bit bit bit 1024-bits 2 vector load/store units SuperGather Bus interface idma Target frequency Optional 32 non-contiguous locations read/written per instruction AXI4 no alignment restrictions, local memory to local memory transfers, nm nm Vector floating point, ECC Dream Chip Technologies Confidential 14
15 Dream Chip Technologies Confidential Dream Chip Technologies GmbH
16 Why CNNs? [Kaiming He, Xiangyu Zhang, Shaoqing Ren, & Jian Sun. Deep Residual Learning for Image Recognition. CVPR 2016.] Human: 5.1% Dream Chip Technologies Confidential 16
17 Why CNNs? ADAS video applications using CNNs Traffic sign recognition Pedestrian detection Image segmentation / Scene labeling Object localization Self driving cars Dream Chip Technologies Confidential 17
18 What is a CNN? Special case of a neural network a deep learning based approach for highquality object detection Neural network: System of interconnected artificial neurons inspired by biological neural system Neurons are the basic computation units of the brain connected with synapses Connections have numeric weights, tuned during training process Properly trained network will respond correctly when presented image or pattern to recognize Drawing of biological neuron Mathematical model of neuron Dream Chip Technologies Confidential 18
19 What is a CNN? cont. Neural network organized in multiple layers Fully connected layers CNNs have additional layers Convolutional layers Pooling / subsampling layers Non-linear layers Dream Chip Technologies Confidential 19
20 What is a CNN? cont. Convolutional layer: Motivated by visual cortex Contains cells responsible for detecting light in small, overlapping sub-regions of the visual field, called receptive fields k x k x D multiply-accumulates (MAC) required to create one element of one output feature Convolution outputs 3-dimensional Multiple convolutional layers Results in a lot of MACs per image (see next slide) Dream Chip Technologies Confidential 20
21 AlexNet CNN 5 convolutional layers 3 fully connected layers 60M weighs ~800M multiply-accumulate to process one 227x227x3 image Trigger function ReLU: f(x)=max(0,x) Dream Chip Technologies Confidential 21
22 The SIP Dream Chip Technologies GmbH Dream Chip Technologies Confidential
23 Assembling the SOM... Dream Chip Technologies GmbH Dream Chip Technologies Confidential
24 System on Module Overview DCT ADAS Heterogeneous Multi-Core Chip (22nm FDSOI Global Foundries) Board-to-board header with chip interfaces Expandable flash storage Power management and measurement Real Time Clock (RTC) Chip power supplies included Benefits Reduced application-specific baseboard complexity Interfaces customizable to application requirements Expandable application flash storage Power consumption measurement Only Single 12 VDC power supply required System-on-Module features Embedded 4GB LP-DDR RAM 128MB ARM Cortex A53 storage 32MB ARM Cortex R5 storage Gigabit Ethernet PHY Power Management IC Real Time Clock (RTC) Interfaces Four 300MB/s video input interfaces One 300MB/s video output interface Gigabit Ethernet Dual Quad-SPI for application storage UART, I2C, SPI, and GPIO Dimensions 194mm x 100mm Dream Chip Technologies Confidential 24
25 4xHDMI Application Board Overview DCT ADAS Quad-HDMI Base Board Four HDMI 1.4b inputs One HDMI 1.4 output Custom high-speed headers available Remote power management Periodic power measurement Gigabit Ethernet CAN 2.0B USB UART Video Genlock generation Benefits Official reference design Prepared for custom sensor interfaces Remote system control Base board features Four ADV7611 HDMI 1.4b receivers One ADV7511 HDMI 1.4 transmitter Video data rates up to 1080p60 Two Intel MAX10 10M08DC FPGAs Four high-speed interface headers MCP2515 CAN 2.0B controller Gigabit Ethernet jack for SoM Micro-USB UART to SoM Micro-USB to System Controller Video Genlock generation Video input synchronization True output genlock possible Dimensions 200mm x 180mm Dream Chip Technologies Confidential 25
26 Software Development Kit Overview DCT ADAS Software Development Kit LEDE distribution with stable Linux bit and 64-bit flavors available Tensilica LX7-IVP6 development support Kernel API drivers Benefits Official Software Development Kit Kernel drivers available Video buffer framework Multi-core processing examples SDK features Complete ARM build environment LEDE distribution (lede-project.org) GNU ARM gcc Linux u-boot musl libc bit and 64-bit flavors all changes against respective mainline versions Kernel Drivers for QSPI, UART, I2C, Ethernet video framework Tensilica LX7-VP6 support Firmware control Debug access Dream Chip Technologies Confidential 26
27 Timeline, next steps FDSOI Technology Development (ST, GF) 28nm (ST) 22nm (GF) Forerunner (DCT) 12nm (GF) Tape Out1 Tape Out2 Prototype 1 Tape Out3 (planning) Prototype 2 Dream Chip Technologies Confidential 27
28 Upcoming: MWC Demo (IMS LUH) Dream Chip Technologies GmbH Dream Chip Technologies Confidential
29 Thank You! Please contact Dream Chip Technologies GmbH Steinriede 10 D Garbsen/Hannover Germany Dream Chip Technologies Confidential
A new Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FDSOI SOI Symposium Santa Clara, Apr.
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