SDIP ASIC Update Tensilica Day Hannover Martin Zeller (DCT)

Transcription

1 SDIP ASIC Update Tensilica Day Hannover 2018 Martin Zeller (DCT)

2 DCT Company Profile Dream Chip Technologies Positioned as a Fabless Microelectronic Engineering Company for medium to large SoC designs covering the whole range from Architecture, Specification, Design, Verification to GDSII Technologies: 130nm, 40nm, 28nm, 22nm FDX, 14/16nm FF > 70 Employees/ 62 Engineers with years SoC design experience Based in Hanover (HQ) and Hamburg, Germany Member of Silicon Saxony/ Germany Cadence Design Center Partner for Tensilica Dream Chip Technologies 2

3 Dream Chip Technologies Target Applications

4 Dream Chip Technologies

5 Dream Chip Technologies MPSoC Chip Architecture

6 CTRL-IO Lockstep PVCI P Lock-Step Other Interrupt Sources SP L1$ ARM R 5 TCMA Host CTRL TCMB SP L1$ ARM R 5 TCMA Host CTRL TCMB Lockstep Low Power CNN Architecture VP6: Pixel Level DMA ARM PL330 IRQ Data Buffer ICache Connection Matrix (SCU.IAC) Module & GPIO Out => CPU Interrupt Inputs A53: Object Level AP ARM A53 High Level Object Proc. C O R E I$/D$ C O R E C O R E C O R E I$/D$ I$/D$ I$/D$ L2 Cache DSP Tensili ca Vision P6 Low Level Pixel Vector Proc. C B O X CTRL-IO TIE DMA DMEM DMEM DMEM DMEM IMEM idma 4x LMEM 4x AXI 32 AXI128 AXI128 AXI128 AXI128 AXI128 OCP128 S C U. P M M S C U. P L L S C U. C R G APB AXI AXI AHB 32 AXI 64 AXI 64 FlexNOC Network on Chip 4x AXI 64 APB AXI 64 AXI 64 AXI 64 APB APB APB APB APB AXI 64 AXI 64 Internal Clocks and Enabling AXI tp PVCI PVCI Reg Clock Int. GPIO STD I/O c LPDDR4 Controll 32bit LPDDR4 PHY c LPDDR4 Controll 32bit LPDDR4 PHY P DMA Hardware Engines HE4 (DEC) P DMA Hardware Engines HE3 (FE) P DMA Hardware Engines HE2 (MD) P MIPI DMA Hardware Engines Group 1 (4xISP) HEs: Pixel Level Memory IF MIPI PHY PAR STD I/O P I2C (4x) STD I/O P P P P P P E P S S U T U C P P A H S I I I R AVB B E S M T MII (2x) (6x) STD I/O USB PHY PCIe PHY STD I/O P G P I O P C A N STD I/O P V D U DSI Tx MIPI PHY P V D U STD I/O I/O IF Dream Chip Technologies 6

7 Dream Chip Technologies SDIP ASIC Design Flow

8 Verification Concept Cadence Incisive Verification Tool Chain Dream Chip Technologies 8

9 SDIP Verification Concept Cadence Incisive Verification Tool Chain Chip-level and sub-system verification UVM SystemVerilog based verification environments Verification environment are configurable to select between usage of IP simulation models or IP RTL For environments hosting a processor this flexibility allows simulation running real program code or generating directed bus transactions. Dream Chip Technologies 9

10 SDIP Verification Concept Cadence Incisive Verification Tool Chain Sub-system environments available for Application processor unit (APU, including ARM A53) Safety processor unit (SPU, including ARM Cortex R5 lockstep) Digital signal processor unit (DSP, including Xtensa VP6) Memory control unit (DDRC, including DDR controller and PHY model) Dream Chip Technologies 10

11 APU Verification Environment (Flavour A) APB Slave UVC APB IF (dbg) AXI IF (ddr) AXI Master UVC APB Slave UVC apu_ca53_smod (replaces apu_ca53) APU Sideband Env Sideband Sideband Interface Interfaces AXI IF (acp) SB SB UVC UVC p p p p p APB IF (cfg) AXI Slave UVC p APU APU Env Config : use_smod == true tb_level == chip DMA-330 APU_NOC GIG-400 Environment configured to be used on chip-level using the A53 simulation model A53 APB and AXI transfers driven by according UVC sequences Remaining sideband port are driven by sideband UVCs Dream Chip Technologies 11

12 APU Verification Environment (Flavour B)) Virtual Sequencer APB Master UVC APB IF (dbg) APB (slv) AXI (mst) p AXI IF (ddr) AXI Slave UVC APB Master UVC APB IF (cfg) apu_ca53 APU Sideband Env SB SB UVC UVC Sideband Sideband Interfaces Interfaces p p p p APB (slv) Optional monitor (passive) Sidebands AXI IF (acp) AXI Slave UVC p Clock & Reset Env Clock & Reset Interfaces p System Scoreboard Reg Model (optinal) NSP (mst) DMA-330 p nsp2axi AXI IF AXI Slave UVC APU_NOC APU Env Config : use_smod == false tb_level == block GIG-400 p axi2nsp AXI IF AXI Master UVC apu_tb / sdip_tb APU NSP (slv) uvm_test Environment configured to be used on subsystem-level using the A53 RTL A53 APB and AXI transfers driven C program code Remaining sideband port are driven by IP itself Dream Chip Technologies 12

13 SDIP Chip-Level Verification Environment SPU Env (passive) APU Env (passive) DSP Env (passive) SDIP_CHIP Env (UVM) SPU Env (active) APU Env (active) DDR Env (active) DSP Env (active) Reg Model (optinal) CR5 interfaces A53 interfaces DDR Mem Model DSP interfaces SDIP_CHIP System Scoreboard Flash Mem Model Boot Flash (SPIM) CR5 IFs CR5 SMOD CR5 RTL SPU A53 IFs A53 SMOD A53 RTL APU DDR IFs DDR SMOD DDR RTL DDR DSP IFs DSP SMOD DSP RTL DSP NOC Virtual Sequencer Flash Mem Model BootFlash (SPIM) LPIO Camera IF Stream IO PLL Eth GPIO UART I2C SPIS JTAG VDU LPIO Interfaces (GPIO, UART, I2C, SPI, JTAG) FrameGen IFs Clock & Reset Interfaces Pin Check LPIO Env VideoIn Clock Env Clock & Reset Env uvm_test SDIP_CHIP Testbench Dream Chip Technologies 13

14 Dft and Backend Cadence Genus/Modus/Innovus Backend Tool Chain Dream Chip Technologies 14

15 SDIP Chip: Layout Overview Cadence Innovus Backend Tool Chain GF 22FDX technology PDK v0.5_ track library 7885,3µm x 8001,3µm 10LM Flipchip 1292 bumps 405 signal IOs 150um/200um pitch LVT/SLVT + FBB up to 1 GHz 0.8V core / 1.8V IO Dream Chip Technologies 15

16 SDIP Chip: Design Info Cadence Innovus Backend Tool Chain ~15.6M Instances LPDDR1 ~11.6mm² RAM 489 insts / 7426 kbytes only 9 different RAM cells Prepared for FBB Timing Optimization One SDC only 4 setup analysis views 9 hold analysis views DSP 4 x IVP6 A53 LPDDR0 R5 PLL Dream Chip Technologies 16

17 SDIP Chip: Hierarchical Layout with Innovus Cadence Innovus Backend Tool Chain sdip_chip ARM A53 4 x A53 CPU ARM R5 DSP 4 x Tensilica VP6 2 x 32bit LPDDR4 5 x PLL DSP 4 x VP6 LPDDR1 A53 Quad 4x A53 + L2 PLLs R5 LPDDR0 Dream Chip Technologies 17

18 Layout Runtime Info Cadence Innovus Backend Tool Chain A53 CPU 12h A53 Quad 12h VP6 60h DSP 30h R5 lockstep 17h SDIP chip 70h total 160h 3 x Intel(R) Xeon(R) CPU E GHz (12 Cores / 256GB RAM) 5 x Intel(R) Core(TM) i7-6700k 4.00GHz (8 Cores / 128GB RAM) multiple small machines organized as SunGridEngine Dream Chip Technologies 18

19 Static Timing Analyses Cadence Tempus Hierarchical Approach A53 Quad DSP R5 lockstep SDIP chip 34 Scenarios 6h runtime / 4 DMMC Jobs (8 CPUs each) Dream Chip Technologies 19

20 Layout Verification 3 rd Party Toolchain Cadence PVS was not qualified for signoff at TO time Hierarchical Approach not possible for sign-off high run time DRC 72h (3 x 12 CPUs / > 1TB RAM) LVS 3h FILL 89h (runset not prepared for massive parallel computing) Dream Chip Technologies 20

21 Dream Chip Technologies Power Analyses

22 Differential power analysis / Processors Heavy computing on one A53 at 500MHz adds +90mW P(core) Each additional heavy computing A53 at 500MHz core adds +25mW P(core) Heavy computing on VP6 RISC at 500MHz adds +290mW P(core) Heavy computing on VP6 SIMD at 500MHz adds +975mW P(core) A53/VP6 RISC computing: Mersenne Twister pseudo-random number generator VP6 SIMD computing: Vector multiplication Dream Chip Technologies 22

23 Differential power analysis DDR One LPDDR at 1066MHz adds +715mW P(total) Second LPDDR at 1066MHz adds +300mW P(total) Using LPDDR at 1333MHz adds +150mW P(total) per controller Dream Chip Technologies 23

24 Differential power analysis / Demos Multiview application runs at +300mW P(total), +190mW P(core) Topview application runs at +450mW P(total), +350mW P(core) Topview computing consumes 165mW P(core) Dream Chip Technologies 24

25 Dream Chip Technologies SDIP ES 3.0 -> 2018

26 Roadmap / Technology Improvements GF 22 nm FDSOI PDK 1.2 better PPA use 8-track libraries fix DDR phy weaknesses Power Management Optimization restrict use of LVDS cells Flow use new Cadence LBIST flow use Cadence PVS for DRC / LVS sign-off use hierarchical sign-off and fill flow Dream Chip Technologies 26

27 Roadmap / Features Replace two Vision P6 by Vision C5 Processors Add USB interface Add 2D GPU Minor bug fixes / improvements Dream Chip Technologies 27

28 Dream Chip Technologies Demos

29 Dream Chip Technologies Demo (Tensilica Day LUH)

30 Dream Chip Technologies Demo (In Dreamchip)

31 Dream Chip Technologies Thank You! martin.zeller<at>dreamchip.de Steinriede 10 D Garbsen/Hannover Germany

32 Dream Chip Technologies MPSoC Chip / Starter Kit

33 Dream Chip Technologies The SIP System-on-Module features 4GB LP-DDR RAM Interfaces Four 300MB/s video inputs One 300MB/s video output Gigabit Ethernet

34 Dream Chip Technologies Assembling the SOM... Overview Power management and measurement Chip power supplies included Benefits Reduced application-specific baseboard complexity Interfaces customizable to application requirements

35 4xHDMI Application Board Overview DCT ADAS Quad-HDMI Base Board Four HDMI 1.4b inputs One HDMI 1.4 output Custom high-speed headers available Base board features Video data rates up to 1080p60 Two Intel MAX10 10M08DC FPGAs Four high-speed interface headers Video input synchronization True output genlock possible Dream Chip Technologies 35

36 Software Development Kit Debug Access Secure TrustZone PSCI API ARM Cortex-A53 Multi-Core User Application Linux Kernel Kernel Drivers Video4Linux API Tensilica LX7-VP6 Multi-Core User Application Mailbox API Overview DCT ADAS Software Development Kit LEDE distribution with stable Linux bit and 64-bit flavors available Tensilica LX7-IVP6 development support Kernel API drivers ARM Cortex-R5 Lock-step CPU Communication Interfaces Video Input Interfaces Video Output Interface SDK features video framework Tensilica LX7-VP6 support Dream Chip Technologies 36