A new Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FDSOI SOI Symposium Santa Clara, Apr.

Transcription

1 Dr. Jens Benndorf MD, COO Dream Chip A new Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FDSOI SOI Symposium Santa Clara, Apr. 13th, 2017

2 DCT Company Profile Dream Chip Technologies Positioned as a Fabless Microelectronic Engineering Company for medium to large SoC designs covering the whole range from Architecture, Specification, Design, Verification to GDSII Technologies: 130nm, 40nm, 28nm, 22nm FDX, 14/16nm FF 60 Employees/ 52 Engineers with years SoC design experience Based in Hanover (HQ) and Hamburg, Germany Member of Silicon Saxony/ Germany Cadence Design Center Partner for Tensilica

3 Assisted Driving requires Cameras, Radar and Ultrasonic Source: Texas Instruments

4 Use Case #1: Digital Mirroring Source:

5 Use Case #1: Digital Mirroring - The Multiview Automotive multi camera systems for Bird-View, Rear-View and Panorama- View are a major part of today s emerging technologies to make driving more safe and comfortable and to move towards autonomous vehicles.

6 Target Applications Automotive Camera-Monitor-Systems, e.g. electronic rear mirror Key Features Works in YUV domain, independent of image sensor Works on flicker frequencies from 80 Hz up Unlimited flickering light sources in image Optimized implementations available for several platforms, including Tensilica Vision P6 TI TDA3 nvidia CUDA RTL (Q2 / 2017) Use Case #1: Digital Mirroring Flicker Mitigation

7 Use Case #2 : 360 deg Top View Camera

8 Use Case #3 : Pedestrian detection via CNNs

9 Partitioning of Algorithms

10 Introduction Image Sensor Processing Overview

11 Heterogeneous Cores for Image Sensor Processing GPU (VP6) A53 DSP (VP6, A53) Vector DSP (VP6, HW)

12 MPSoC Chip Architecture

13 Low Power CNN Architecture Lock-Step A53: Object Level VP6: Pixel Level HEs: Pixel Level I/O IF Memory IF

14 Floorplan Memory IF Tape-Out 10.Jan IVP: Pixel Level Global Foundries 22 FDX GF externally adjustable BIAS voltage 8x8 mm (64 mm^2) Calculation Power ARM Cortex A53 quad core 4x Tensilica Vision P6 optimized for ADAS and CNN 4x video-in, 1x video-out MCM package DIE + 2x DDR4 on Silicon interposer ARM A53: Object L. Lock-Step Memory IF

15 MPSoC Chip / Starter Kit

16 System in Package Design System-on-Module features 4GB LP-DDR RAM Interfaces Four 300MB/s video inputs One 300MB/s video output Gigabit Ethernet

17 Assembling the SOM... Overview Power management and measurement Chip power supplies included Benefits Reduced application-specific baseboard complexity Interfaces customizable to application requirements

18 4 x HDMI Application Board Overview DCT ADAS Quad-HDMI Base Board Four HDMI 1.4b inputs One HDMI 1.4 output Custom high-speed headers available Base board features Video data rates up to 1080p60 Two Intel MAX10 10M08DC FPGAs Four high-speed interface headers Video input synchronization True output genlock possible

19 Demo

20 Mobile World Congress 2017 Demo

21 Thank You! Please contact Steinriede 10 D Garbsen/Hannover Germany