Designing a Multi-Processor based system with FPGAs
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1 Designing a Multi-Processor based system with FPGAs BRINGING BRINGING YOU YOU THE THE NEXT NEXT LEVEL LEVEL IN IN EMBEDDED EMBEDDED DEVELOPMENT DEVELOPMENT Frank de Bont Trainer / Consultant Cereslaan 10b 5384 VT Heesch +31 (0) info@core-vision.nl 1
2 Why Use Processors? Microcontrollers (µc) and microprocessors (µp) provide a higher level of design abstraction Most µc functions can be implemented using VHDL or Verilog Downsides are parallelism & complexity Using C/C++ abstraction & serial execution make certain functions much easier to implement in a µc Discrete µcs are inexpensive and widely used µcs have years of momentum and software designers have vast experience using them 2
3 µp versus µc A microprocessor (µp) is just one component of many in a complex system of digital & analog I/O ROM EEPROM ROM EEPROM RAM ADC DAC I/O Device Microprocessor I/O Device Serial Parallel Timer PWM RAM ADC Microcontroller CPU Core Serial Parallel Timer PWM DAC Most simple system components are contained completely within a microcontroller (µc) 3
4 Rarely the Ideal Mix Difficult to find the required mix of peripherals in Off the Shelf (OTS) microcontroller solutions Today System Requirements UART USB TIMER Ethernet SPI GPIO FLASH DDR Microcontroller #1 FLASH RAM GPIO CPU Core UART USB SPI Timer Lacks Ethernet & Includes RAM vs DDR? Microcontroller #2 FLASH DDR GPIO Ethernet CPU Core UART CAN SPI Timer Lacks USB & Includes Unnecessary IP 4
5 Changing Requirements Difficult to find the required mix of peripherals in Off the Shelf (OTS) microcontroller solutions Selecting a single processor core with long term solution viability is difficult at best Todays System Requirements 1 GHz UART USB TIMER 10/100 Ethernet SPI GPIO FLASH DDR3 FLASH DDR3 GPIO Ethernet Microcontroller 1 GHz CPU Core UART USB SPI Timer Meets current system requirements Future System Requirements 2.4 GHz UART USB TIMER 10/ 100/1000 Ethernet SPI GPIO FLASH DDR4? 5
6 Here Today, Gone Tomorrow Difficult to find the required mix of peripherals in Off the Shelf (OTS) microcontroller solutions Selecting a single processor core with long term solution viability is difficult at best Without direct ownership of the processing solution, obsolescence is always a concern FLASH DDR3 GPIO Ethernet? 1 GHz CPU Core FLASH DDR3 GPIO Ethernet UART 1 GHz CPU Core UART FLASH SPI DDR3 Timer GPIO Ethernet USB UART 1 GHz CPU Core SPI Timer Microcontroller #1 - Low Volume Niche Microcontroller #2 Moderate Volume Microcontroller #3 High Volume Automotive USB CAN SPI Timer 6
7 Chipset Solutions Difficult to find the required mix of peripherals in Off the Shelf (OTS) microcontroller solutions Selecting a single processor core with long term solution viability is difficult at best Without direct ownership of the processing solution, obsolescence is always a concern Many microprocessor based solutions provide limited On-Chip peripheral support 1 GHz CPU Core Microprocessor Chip-Set Pre-defined interface limits performance Proc Interface Serial Parallel PWM I/O Expansion Device 7
8 Embedded Design with FPGAs FPGA allow for the implementation of an ideal mix of peripherals and system infrastructure New system requirements can be supported without changing the processor core Longevity of FPGAs approaches the longest available microcontrollers in the market FPGAs are used to augment µp functionality absorbing the core is the next natural step 8
9 Simple Processor System clock reset CPU Core interrupts Processor Core Arbiter Primary Bus Bridge Secondary Bus Arbiter System Infrastructure FLASH DDR Timer UART System Peripherals 9
10 Softcore Processor System clock reset Processor Core BRAM ILMB Bus DLMB Bus BRAM System Infrastructure interrupts AXI Interconnect INTC System Peripherals FLASH DDR Timer UART GPIO 10
11 Hybrid Processor System FLASH DDR3 clock emmc QSPI DDR3 reset interrupts Processor Cores imx6 System Infrastructure CVBS / HD-SDI Ethernet Switch UART USB RS-422 HDMI Ethernet UART USB Camera Link Motor Control System Peripherals 11
12 Hybrid Processor System FLASH DDR3 clock emmc QSPI DDR3 reset interrupts Processor Cores imx6 System Infrastructure CVBS / HD-SDI Ethernet Switch UART USB RS-422 HDMI Ethernet UART USB Camera Link Motor Control System Peripherals 12
13 FPGA based Processor System emmc QSPI DDR4 clock reset Processor Core interrupts UART USB RS-422 HDMI Ethernet Camera Link Motor Control CVBS / HD-SDI System Peripherals 13
14 FPGA based Processor System Processing System Application Processing Unit ARM Cortex -A53 32 KB I-Cache w/parity 32 KB D-Cache w/ecc clock reset interrupts NEON Floating Point Unit Memory Management Unit Embedded Trace Macrocell GIC-400 SCU CCI/SMMU 1 MB L2 w/ecc Real-Time Processing Unit ARM Cortex -R5 128 KB TCM w/ecc GIC 32 KB I-Cache w/ecc Vector Floating Point Unit Memory Protection Unit 32 KB D-Cache w/ecc emmc QSPI Memory DDR4/3/3L, LPDDR4/3 ECC Support 256 KB OCM with ECC Platform Management Unit System Management Power Management Functional Safety DDR4 Graphics Processing Unit ARM Mali -400 MP2 Geometry Processor Memory Management Unit Configuration and Security Unit Config AES Decryption, Authentication, Secure Boot Voltage/Temp Monitor TrustZone 64 KB L2 Cache Pixel Pixel Processor Processor 1 2 System Functions Processor Core Multichannel DMA Timers, WDT, Resets, Clocking, & Debug High-Speed Connectivity (Up to 6Gb/s) DisplayPort USB 3.0 SATA 3.1 PCIe 1.0 / 2.0 General Connectivity GigE USB 2.0 CAN UART SPI Quad SPI NOR NAND SD/eMMC Programmable Logic Storage & Signal Processing Block RAM General-purpose I/O UART USB RS-422 HDMI UltraRAM DSP High-Performance I/O High Density (Low Power) I/O Ethernet System Peripherals High-Speed Connectivity 16G Transceivers Camera 33G Link Transceivers Interlaken 100G EMAC Motor Control PCIe Gen4 CVBS / HD-SDI Video Codec H.265/H.264 AMS 14
15 Necessary Tools A full complement of tools are required to design an embedded processor system Processor system generation Hardware implementation tools Software compilers Hardware debugger tools Software debugging tools clock reset interrupts emmc QSPI DDR4 UART USB RS-422 HDMI Ethernet Camera Link Motor Control CVBS / HD-SDI 15
16 Necessary Tools A full complement of tools are required to design an embedded processor system Processor system generation Hardware implementation tools Software compilers Hardware debugger tools Software debugging tools clock emmc QSPI DDR4 reset interrupts HW implementation & SW compilation are the two main flows that must be addressed The embedded flows should mirror traditional flows UART USB RS-422 HDMI Ethernet Camera Link Motor Control CVBS / HD-SDI 16
17 Traditional Embedded Design Flow C Code VHDL or Verilog Standard Embedded SW Development Flow Embedded Developers Kit Standard FPGA HW Development Flow Code Entry C/C++ Include Cross the Compiler BSP and Compile the Software Linker Image Board Support Package Data2MEM System Netlist HDL Entry Instantiate the Simulation/Synthesis System Netlist and Implement Implementation the FPGA? 2 Compiled ELF 3 Compiled BIT 1? Load Software Into FLASH Debugger Download Combined Image to FPGA Download Bitstream Into FPGA ILA SDK RTOS, Board Support Package Vivado 17
18 Design Flow and Tools Software Real-time OS Drivers APIs... Tools Vivado SDK Matlab SDSoC... FPGA hardware Spartan - Artix Kintex - Virtex Zynq S Zynq UltraSCALE + Dual A53 / Dual R5 Quad A53 / Dual R5 / Codec Quad A53 / Dual R5 / GPU Tools Vivado HLx Matlab... 18
19 1-2 4 Embedded Design Flow with SDSoC Migrate C/C ++ functions to hardware System-level debug and profile Simple hardwaresoftware partitioning Full system generation including driver and hardware connectivity Performance Estimation C/C++ Applications System-level Profiling Specify Functions for Acceleration Full System Generation 19
20 Design Flow without SDSoC System Spec (C/C++) HW / SW Partition HW Design (Verilog / VHDL / HLS) Vivado / HLS IP IP PL HW Connectivity (IPI Block Design) Vivado IPI Data path SW Driver (Low-level C) SDK / OS Tools Drivers / Middleware SW Connectivity (C/C++) Req. Met? SDK Application PS 20
21 Design Flow with SDSoC System Spec (C/C++) Function Selection IP IP PL Refine Code Glue Logic Req. Met? Code typically needs to be refined to achieve optimal results Driver / Middleware Application PS 21
22 SDSoC System Level Profiling Rapid system performance estimation Full system estimation (programmable logic, data communication, processing system) Reports SW/HW cycle level performance and hardware utilization Automated performance measurement Runtime measurement by instrumentation of cache, memory, and bus utilization 22
23 **slide MPSoC HW/SW Considerations Quad-core ARM Cortex-A53 Dual-core ARM R5 ARM Mail-400MP GPU DDRx and SMC controllers Security firmware Platform Management Unit FSBL, uboot ARM trusted firmware XEN hypervisor Software test libraries Inter-processor Framework Multi-OS boot image 23
24 105022**slide Example Default Configuration: APU-Linux / RPU System software FSBL: First Stage Boot Loader uboot: Open source APU: Non-secure mode RPU ARM trusted firmware: From Xilinx, verified on APU SMP Linux No hypervisor: Non-secure mode In split mode (default) R5-0: FreeRTOS R5-1: Bare-metal 24
25 105022**slide Example Configuration: APU-Hypervisor Linux / RPU System software FSBL: First Stage Boot Loader uboot: Open source APU: Non-secure mode ARM trusted firmware/xen hypervisor, verified on APU Guest OS Domain (1): Linux Domain (2): Bare-metal RPU In split mode (default) R5-0: FreeRTOS R5-1: Bare-metal 25
26 1-3 8 Run-Time Software 26
27 Qemu Emulation Platform QEMU emulation platform Provides Linux hosted emulation platform Accelerates and scales embedded software development Enables architecture and porting of software Emulates multiple blocks of the processing system QEMU enables you to start working on designs before hardware is available 27
28 1-8 How Qemu Works 28
29 Core Vision Our competences Core Vision has more than 125 man years of design experience in hard- and software development. Our competence areas are: System Design FPGA Design Consultancy / Training Digital Signal Processing Embedded Real-time Software App development, IOS Android Data Acquisition, digital and analog Modeling & Simulation PCB design & Layout Doulos & Xilinx Training Partner 29
30 Q&A Cereslaan 10b 5384 VT Heesch +31 (0) info@core-vision.nl 30
31 Visit our booth 11 31
32 Training Program Essentials of FPGA Design Designing for Performance Advanced FPGA Implementation Design Techniques for Lower Cost Designing with Spartan-6 and Virtex-6 Family Essential Design with the PlanAhead Analysis Tool Advanced Design with the PlanAhead Analysis Tool Xilinx Partial Reconfiguration Tools and Techniques Designing with the 7 Series Families 1 day 1 day 3 days 1 day 32
33 Training Program Designing FPGAs Using the Vivado Design Suite 1 Designing FPGAs Using the Vivado Design Suite 2 Designing FPGAs Using the Vivado Design Suite 3 Designing FPGAs Using the Vivado Design Suite 4 Designing with the UltraScale and UltraScale + Architecture Vivado Design Suite for ISE Software Project Navigator User 1 day Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software User 33
34 Training Program Designing with Multi Gigabit Serial IO 3 days High Level Synthesis with Vivado C-Based HLS Coding for Hardware Designers 1 day C-Based HLS Coding for Software Designers 1 day DSP Design Using System Generator Essential DSP Implementation Techniques for Xilinx FPGAs 34
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36 Training Program VHDL Design for FPGA Advanced VDHL Comprehensive VHDL Expert VHDL Verification Expert VDHL Design Expert VHDL Essential Digital Design Techniques 3 days 5 days 3 days 5 days 36
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