XEEMU: An Improved XScale Power Simulator
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1 Department of Software Engineering (1), University of Szeged Department of Electrical Engineering (2), University of Kaiserslautern XEEMU: An Improved XScale Power Simulator Z. Herczeg(1), Á. Kiss (1), D. Schmidt (2), N. Wehn (2), T. Gyimóthy (1) PATMOS
2 Overview Motivation Necessity of a realistic power simulator Implementation of XEEMU Experimental results Conclusion 2
3 Introduction Energy efficiency is one of the top priorities in embedded systems design Understanding power consumption is mandatory for the design of efficient power management schemes Power Simulators allow designers to accurately predict power/energy consumption compare two competing approaches create realistic, higher abstraction level power models We present XEEMU, a fast and highly accurate simulator for the XScale architecture, including a SDRAM memory subsystem 3
4 Why another simulator? Power management frequently relies on simple assumptions: P f V 2 dd E f V 2 dd t Arbitrary voltage levels may be used Voltage changes take no-time System power consumption in Idle state negligible Only CPU energy consumption is considered and optimized 4
5 Test Setup - Sanity check ADI 80200EVB evaluation board Intel XScale processor, 266 to 733 MHz in 66MHz steps ARM compatible, pipelined RISC architecture 32 MByte Micron SDRAM, 100 MHz Additional HW for voltage scaling in three steps Measurement taps for CPU core current, IO current, system peripherals Very simple CRC benchmark code and data fit completely into the cache No operating system running on the processor Digital Storage oscilloscope Repeated measurements and averaged results to reduce noise in the samples 5
6 CPU Energy Measurements Energy optimal point ADI EVB XScale Board, Core Energy Consumption 6
7 Taking the System into Account Energy optimal point Same Test Setup as Before Including Peripheral Energy (32MByte SDRAM) 7
8 Accounting for Idle Time Energy optimal point 8
9 Lessons Learned Higher frequencies can be energy efficient In modern technologies static power consumption is non-negligible Idle-Time power consumption is non-negligible You have to take into account the whole system Voltage and Frequency Scaling does not affect memory subsystem No available simulator does that Design goals for XEEMU Accurate system simulation for processor and memory subsystem 9
10 XTREM (Contreras et al.) Memory latency (measured): 78 to 126 Clock Cycles Partially hidden by XScale (not simulated by XTREM) XTREM is accurate if you match up one error by fine tuning another! 10
11 XEEMU Runtime Model Behavioral Model of each pipeline stage Based on documentation, where available Validated and improved by synthetic stress marks Focus on one certain part of the processor Use XScale built in clock counters for evaluation Many errors in XTREMs model were discovered Cycle accurate simulation of SDRAM subsystem Seperately configurable clock domain Considering effects of refresh, open rows, etc. 11
12 XEEMU Power Model Analytical power model for caches is inherited from Sim- Panalyzer Pipeline stages are modeled using empirical power models Requires no knowledge of production process or internal structure Parameters are fitted to match measurements on the evaluation board This is done using activity traces and power charts SDRAM power model obtained directly from Micron Not validated by time of publication Assumes worst case power 12
13 Results: Runtime and Energy Average error: 3.0% (runtime) 1.6% (energy) 13
14 Results: Insantaneous Power 14
15 Results: Simulation Speed 15
16 Conclusions and Future Work Traditional, simple power models are misleading! Traditional power simulators focus on CPU power only XEEMU is the most accurate available XScale simulator First simulator to integrate CPU and SDRAM simulation Only 3.0% and 1.6% avg. error for runtime and power simulation Freely available under GPL Source and binary downloads under XEEMU is still under development Accurate modeling of DVFS will soon be added 16
17 Thank you! Questions? Please visit our website: 17
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