EE Embedded Systems Design

Size: px
Start display at page:

Download "EE Embedded Systems Design"

Transcription

1 EE Embedded Systems Design Lesson 2 Structured Design, Documentation, and Laboratory Notebooks 1 Overview - Structured Design The divide-and-conquer technique Requirements Partitioning - The Black Box Structure Chart Pseudo (Fake) Code Implementation Techniques Testing Techniques Documentation Unified Modeling Language (UML) 2

2 Challenges in Embedded System Design Hw much hardware do we need: too little H/W and the system may fail to meet requirements, too much leads to expensive system How do we meet the deadline: Brute force (get the fastest H/W) leads to expensive system, Better design How to minimize power consumption: reduce the speed, that is guaranteed to reduce power. Better careful design to identify the noncritical parts for power consumption 3 Challenges in Embedded System Design How to design for upgradeability: Several different version of the product could be designed (different prices). Can we use the same H/W? S/W? Does it really work? How to be sure that it works as requested If workstation programming is like assembling a machine on a bench, embedded system design is like working in a car, cramped, and difficult 4

3 Challenges in Embedded System Design Testing: More difficult than traditional computing system We may have to run the machine the system is embedded in Timing plays a very important role Limited observability and controllability No keyboard or CRT Restricted development environments 5 The divide-and-conquer technique Paper writing/book writing Solid outline allows big picture view Write a paragraph at a time Use same technique in SW/HW design divide project into understandable, doable pieces A.K.A.: top-down-design, bottom-upimplementation... 6

4 Requirements Overall goal of structured design is to provide tools to transform system requirements into a plan to implement a system Your responsibility to ensure you understand requirements iterative process with customer More difficult if the customer is not an engineer 7 Requirements Requirements may be functional or nonfunctional (performance, cost, physical size and weight) Validating requirements: very difficult, may require to build a mock-up. For example a small program running on a PC with the required user interface so the customer may test drive it 8

5 Simple Requirements Form Name: Purpose Inputs Outputs Functions Performance Cost Power Physical size and weight 9 Requirements In a large project, a more thorough requirements analysis is done. The previous form may act as a summary of a much longer requirements documents. After you finish the requirements, check for inconsistency? Any unrealistic features in a cheap product, large power consumption in a portable product? 10

6 Partitioning - The Black Box Break a large, complex system into a hierarchical description of black boxes black box : small definable pieces know inputs, outputs, general details of function define relationship between black boxes use a graphical tools relationship Structure Chart provides big picture 11 Structure Chart 12

7 Modeling Structured chart describe the big picture. Not very useful for small systems. Unified Modeling language UML activity chart Flow chart is used to model flow of control Pseudocade 13 Pseudo (Fake) Code Once hierarchy is defined begin working out details of black box. Develop functional relationship between the boxes inputs and outputs Use pseudocode to defer details not trying to avoid details defer until higher level details worked out 14

8 Implementation Techniques Incremental Approach - get a little bit working at a time Top-down: implement top module lower level code simulated with stubs (empty modules) Bottom-up: implement module at lowest level. Higher level code simulated with drivers Hybrid: use of mixture of both techniques and meet in the middle 15 Testing Techniques Compile time errors Run Time errors Everything is O.K. except project completed to incorrect requirements!!! Test Plan Test each subpart separately Test after integration 16

9 Documentation External documentation - support information Structure Chart Internal documentation Comments Self-documenting code - wise choice of variable, function names Program Formatting - pretty printing - use blank spaces to help illustrate the control structure of the program 17 Unified Modeling Language (UML) Standardized set of graphical tools to model a complex system prior to implementation Used in structural description, behavioral description, and specification Used to describe object-oriented design Activity Diagram -- UML-compliant flow chart 18

10 Unified Modeling Language (UML) 19 Laboratory Notebooks Legal document - may be used in court to establish ownership of an idea Mechanics Use ink, must be bound Number each page consecutively, use both sides Sign and date each page Glue additional figures into notebook - sign and date Z out unused space Do not remove incorrect material - X it out 20

11 Cont. Laboratory Notebooks What to include? Everything Flowcharts of any non trivial procedures Program listing, printout and glued. A narrative of what you did, including mistakes New page for every day 21 Flowchart main Count=0 Count=count+1 <10 pulse pulse PORTB=1 PORTB=0 return void pulse(void) { PORTB=1 PORTB=0 } void main(void) { int counter; while(1) { count=0; do{ count++; } while(count<10) pulse(); } } 22

12 Requirements New requirements Product Development Cycle Analyze the problem Specifications Constraints High-level Design Block diagram Data flow graphs Not Done Engineering Design Testing Implementation Done Hardware Software Call graphs Data structure I/O Interface 23 High-level-design: Thermometer Build a conceptual model of the hardware/software system Mainly abstraction, no details Divide the system into modules and subcomponent Dataflow graphs are a good tool to use in this stage 24

13 Thermometer Temperature Temperature sensor voltage Analog amplifier voltage ADC Timer Fixed-point temperature Digital samples LCD Display LCD Routines Temp calculation Fixed-point voltage ADC Routines F or C Table lookup Switch 25 Engineering Design HW/SW Division The basic I/O signals Data structure Flowchart for the software part. Call graph The mechanical part design 26

14 Call Graph ADC Timer H/W Main program ADC Routines LCD Routines ADC H/W LCD H/W Switch I/P 27 Implementation Start writing the code and designing the circuits Test every component separately, and again when combined with another component Same for Software Golden rule for S/W: Write software for others as you wish they would write for you You are a good programmer if you can read your code 12 months later and understand it AND others can make changes to your code 28

15 Another Design Process Requirement Specification Architecture Testing and verification at every stage Iterative process Usually top-down design, bottom-up implementation Components Integration 29 GPS Moving Map System is designed for highway driving not aviation use. The system should have the major roads and landmarks The user interface have at least 400x600 pixel resolution. No more than 3 buttons. Menus are used for selection Production cost is $100 Works on battery, and hand-held 30

16 Name: Purpose: Inputs: Outputs: Functions: Requirements Form GPS moving map Consumer-grade moving map for drivers Power button, 2 control buttons back-lit LCD display 400x600 Uses 5-receiver GPS system three user selectable resolution, always display current latitude and longitude Performance Updates screen within 0.25 sec upon movement Cost $100 Power 100 mw Shape&weight No more than 2 x6, 12 ounces 31 Specifications Specifications is more precise, it is the contract between the designer and the customer. Should be understandable enough so that someone can verify that it meets the requirements. Should be unambiguous enough so the designers know what they need to build 32

17 Specifications UML is used to describe objects and classes Each class has a name, attributes and operations. UML is useful at many level of abstractions Successive refinements instead of starting over at each abstraction level. More in the next example. 33 Specifications Display pixels elements menu_items mouse_click() draw_box() A class in UML notations d1: Display Pixels:array[]of pixels Elements menu_items An object in UML notations 34

18 State Machine Specifications mouse_click(x,y,button) find_region(region) region=menu/ Start Which_menu(i) Region Got menu item call_menue(i) Called menu item Stop found region=drawing/ find_object(objid) Found object Object highlighted highlight(objid) 35 Architecture Design 36

19 Hardware Architecture Display Frame buffer Memory CPU GPS receiver Bus I/O Panel 37 Software Architecture Database search Renderer position User interface Timer 38

Design of Embedded Systems

Design of Embedded Systems Design of Embedded Systems José Costa Software for Embedded Systems Departamento de Engenharia Informática (DEI) Instituto Superior Técnico 2015-01-02 José Costa (DEI/IST) Design of Embedded Systems 1

More information

The Embedded System Design Process. Wolf Text - Chapter 1.3

The Embedded System Design Process. Wolf Text - Chapter 1.3 The Embedded System Design Process Wolf Text - Chapter 1.3 Design methodologies for complex embedded systems? Design methodologies A procedure for designing a system. Understanding your methodology helps

More information

The Embedded System Design Process. Wolf Text - Chapter 1.3

The Embedded System Design Process. Wolf Text - Chapter 1.3 The Embedded System Design Process Wolf Text - Chapter 1.3 Design methodologies A procedure for designing a system. Understanding your methodology helps you ensure you didn t skip anything. Compilers,

More information

Introduction. Definition. What is an embedded system? What are embedded systems? Challenges in embedded computing system design. Design methodologies.

Introduction. Definition. What is an embedded system? What are embedded systems? Challenges in embedded computing system design. Design methodologies. Introduction What are embedded systems? Challenges in embedded computing system design. Design methodologies. What is an embedded system? Communication Avionics Automobile Consumer Electronics Office Equipment

More information

Reminder. Course project team forming deadline. Course project ideas. Friday 9/8 11:59pm You will be randomly assigned to a team after the deadline

Reminder. Course project team forming deadline. Course project ideas. Friday 9/8 11:59pm You will be randomly assigned to a team after the deadline Reminder Course project team forming deadline Friday 9/8 11:59pm You will be randomly assigned to a team after the deadline Course project ideas If you have difficulty in finding team mates, send your

More information

Reminder. Course project team forming deadline. Course project ideas. Next milestone

Reminder. Course project team forming deadline. Course project ideas. Next milestone Reminder Course project team forming deadline Thursday 9/6 11:59pm You will be randomly assigned to a team after the deadline Course project ideas If you have difficulty in finding team mates, send your

More information

Formal System Design Process with UML

Formal System Design Process with UML Formal System Design Process with UML Use a formal process & tools to facilitate and automate design steps: Requirements Specification System architecture Coding/chip design Testing Text: Chapter 1.4 Other

More information

Stereotypes. Stereotype: recurring combination of elements in an object or class. Example: <<signal>> mouse_click :

Stereotypes. Stereotype: recurring combination of elements in an object or class. Example: <<signal>> mouse_click : Stereotypes Stereotype: recurring combination of elements in an object or class. Example: mouse_click : Mouse_click (x,y,button) A communication mechanism in Fig 1.11 Computers as Components

More information

UNIT 1 (ECS-10CS72) VTU Question paper solutions

UNIT 1 (ECS-10CS72) VTU Question paper solutions UNIT 1 (ECS-10CS72) VTU Question paper solutions 1. Give the characteristics and constraint of embedded system? Jun 14 Embedded computing is in many ways much more demanding than the sort of programs that

More information

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS ELECTRICAL ENGINEERING DEPARTMENT

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS ELECTRICAL ENGINEERING DEPARTMENT KING FAHD UNIVERSITY OF PETROLEUM & MINERALS ELECTRICAL ENGINEERING DEPARTMENT EE 411 Engineering Design Handout # 2 DESIGN OVERVIEW Engineering design is the creative process of identifying needs and

More information

Choosing IP-XACT IEEE 1685 standard as a unified description for timing and power performance estimations in virtual platforms platforms

Choosing IP-XACT IEEE 1685 standard as a unified description for timing and power performance estimations in virtual platforms platforms hoosing IP-XAT IEEE 1685 standard as a unified description for timing and power performance estimations in virtual platforms platforms Emmanuel Vaumorin (Magillem Design Services) Motivation New needs

More information

Outline. Program development cycle. Algorithms development and representation. Examples.

Outline. Program development cycle. Algorithms development and representation. Examples. Outline Program development cycle. Algorithms development and representation. Examples. 1 Program Development Cycle Program development cycle steps: Problem definition. Problem analysis (understanding).

More information

COMPLEX EMBEDDED SYSTEMS

COMPLEX EMBEDDED SYSTEMS COMPLEX EMBEDDED SYSTEMS Embedded System Design and Architectures Summer Semester 2012 System and Software Engineering Prof. Dr.-Ing. Armin Zimmermann Contents System Design Phases Architecture of Embedded

More information

ECE 587 Hardware/Software Co-Design Lecture 12 Verification II, System Modeling

ECE 587 Hardware/Software Co-Design Lecture 12 Verification II, System Modeling ECE 587 Hardware/Software Co-Design Spring 2018 1/20 ECE 587 Hardware/Software Co-Design Lecture 12 Verification II, System Modeling Professor Jia Wang Department of Electrical and Computer Engineering

More information

Hardware/Software Partitioning of Digital Systems

Hardware/Software Partitioning of Digital Systems Hardware/Software Partitioning of Digital Systems F. Dufour Advisor: M. Radetzki Department of Technical Computer Science University of Stuttgart Seminar Embedded Systems Outline 1 Partitioning and digital

More information

Industrial Embedded Systems - Design for Harsh Environment - Dr. Alexander Walsch

Industrial Embedded Systems - Design for Harsh Environment - Dr. Alexander Walsch Industrial Embedded Systems - Design for Harsh Environment - Dr. Alexander Walsch alexander.walsch@ge.com WS 2011/12 Technical University Munich (TUM) Introduction - Our Backgrounds O&G Energy Sensor systems

More information

Hardware/Software Co-design

Hardware/Software Co-design Hardware/Software Co-design Zebo Peng, Department of Computer and Information Science (IDA) Linköping University Course page: http://www.ida.liu.se/~petel/codesign/ 1 of 52 Lecture 1/2: Outline : an Introduction

More information

Chapter 1 Introduction. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 1 Introduction. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 1 Introduction Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Classes of Computing Applications Hierarchical Layers of Hardware and Software Contents

More information

8.1 Background. Part Four - Memory Management. Chapter 8: Memory-Management Management Strategies. Chapter 8: Memory Management

8.1 Background. Part Four - Memory Management. Chapter 8: Memory-Management Management Strategies. Chapter 8: Memory Management Part Four - Memory Management 8.1 Background Chapter 8: Memory-Management Management Strategies Program must be brought into memory and placed within a process for it to be run Input queue collection of

More information

Memory Management. Memory Management

Memory Management. Memory Management Memory Management Gordon College Stephen Brinton Memory Management Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging 1 Background Program must be brought into memory

More information

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis

More information

Overview of Microcontroller and Embedded Systems

Overview of Microcontroller and Embedded Systems UNIT-III Overview of Microcontroller and Embedded Systems Embedded Hardware and Various Building Blocks: The basic hardware components of an embedded system shown in a block diagram in below figure. These

More information

1. Embedded System Design Process

1. Embedded System Design Process ĐẠI HỌC QUỐC GIA TP.HỒ CHÍ MINH TRƯỜNG ĐẠI HỌC BÁCH KHOA KHOA ĐIỆN-ĐIỆN TỬ BỘ MÔN KỸ THUẬT ĐIỆN TỬ Embedded System Design : Develop a project of embedded system design 1. Design Process 2. Design Issues

More information

Real Time Spectrogram

Real Time Spectrogram Real Time Spectrogram EDA385 Final Report Erik Karlsson, dt08ek2@student.lth.se David Winér, ael09dwi@student.lu.se Mattias Olsson, ael09mol@student.lu.se October 31, 2013 Abstract Our project is about

More information

Chapter 8: Memory Management

Chapter 8: Memory Management Chapter 8: Memory Management Chapter 8: Memory Management Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging 8.2 Background Program must be brought into memory and placed

More information

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Embedded System Design Process Module No: CS/ES/33 Quadrant 1 e-text

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Embedded System Design Process Module No: CS/ES/33 Quadrant 1 e-text e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Embedded System Design Process Module No: CS/ES/33 Quadrant 1 e-text In this lecture various steps involved in Embedded system design

More information

Real Time Operating Systems Application Board Details

Real Time Operating Systems Application Board Details Real Time Operating Systems Application Board Details Hardware Interface All labs involve writing a C program to generate an interface between a PC and an external Multi-Applications board. A 40-way ribbon

More information

Temperature Measurement and Control System Based on Embedded WEB

Temperature Measurement and Control System Based on Embedded WEB Temperature Measurement and Control System Based on Embedded WEB Limin Cai College of Physics and Information Engineering, Jianghan University Wuhan 430056, China Tel: 86-27-8422-6780 E-mail: cailm@yahoo.cn

More information

File Systems. OS Overview I/O. Swap. Management. Operations CPU. Hard Drive. Management. Memory. Hard Drive. CSI3131 Topics. Structure.

File Systems. OS Overview I/O. Swap. Management. Operations CPU. Hard Drive. Management. Memory. Hard Drive. CSI3131 Topics. Structure. File Systems I/O Management Hard Drive Management Virtual Memory Swap Memory Management Storage and I/O Introduction CSI3131 Topics Process Management Computing Systems Memory CPU Peripherals Processes

More information

Module 10: System Integration & Planning. Introduction to I/O Elementary I/O in AVR MSI devices

Module 10: System Integration & Planning. Introduction to I/O Elementary I/O in AVR MSI devices Module 10: System Integration & Planning Introduction to I/O Elementary I/O in AVR MSI devices Introduction Introduction o There are five types of project complexity possibilities: o Purely software o

More information

Computer Architecture. Fall Dongkun Shin, SKKU

Computer Architecture. Fall Dongkun Shin, SKKU Computer Architecture Fall 2018 1 Syllabus Instructors: Dongkun Shin Office : Room 85470 E-mail : dongkun@skku.edu Office Hours: Wed. 15:00-17:30 or by appointment Lecture notes nyx.skku.ac.kr Courses

More information

CSC 121 Spring 2017 Howard Rosenthal

CSC 121 Spring 2017 Howard Rosenthal CSC 121 Spring 2017 Howard Rosenthal Agenda To be able to define computer program, algorithm, and highlevel programming language. To be able to list the basic stages involved in writing a computer program.

More information

Part Three - Memory Management. Chapter 8: Memory-Management Strategies

Part Three - Memory Management. Chapter 8: Memory-Management Strategies Part Three - Memory Management Chapter 8: Memory-Management Strategies Chapter 8: Memory-Management Strategies 8.1 Background 8.2 Swapping 8.3 Contiguous Memory Allocation 8.4 Segmentation 8.5 Paging 8.6

More information

ECE2049: Embedded Systems in Engineering Design Lab Exercise #3 C Term Making a Time and Temperature Display

ECE2049: Embedded Systems in Engineering Design Lab Exercise #3 C Term Making a Time and Temperature Display ECE2049: Embedded Systems in Engineering Design Lab Exercise #3 C Term 2019 Making a Time and Temperature Display In this laboratory you will use the MSP430 and several of its peripherals to implement

More information

HIERARCHICAL DESIGN. RTL Hardware Design by P. Chu. Chapter 13 1

HIERARCHICAL DESIGN. RTL Hardware Design by P. Chu. Chapter 13 1 HIERARCHICAL DESIGN Chapter 13 1 Outline 1. Introduction 2. Components 3. Generics 4. Configuration 5. Other supporting constructs Chapter 13 2 1. Introduction How to deal with 1M gates or more? Hierarchical

More information

Outline HIERARCHICAL DESIGN. 1. Introduction. Benefits of hierarchical design

Outline HIERARCHICAL DESIGN. 1. Introduction. Benefits of hierarchical design Outline HIERARCHICAL DESIGN 1. Introduction 2. Components 3. Generics 4. Configuration 5. Other supporting constructs Chapter 13 1 Chapter 13 2 1. Introduction How to deal with 1M gates or more? Hierarchical

More information

Active-HDL. Getting Started

Active-HDL. Getting Started Active-HDL Getting Started Active-HDL is an integrated environment designed for development of VHDL designs. The core of the system is a VHDL simulator. Along with debugging and design entry tools, it

More information

Operating Systems (2INC0) 2018/19. Introduction (01) Dr. Tanir Ozcelebi. Courtesy of Prof. Dr. Johan Lukkien. System Architecture and Networking Group

Operating Systems (2INC0) 2018/19. Introduction (01) Dr. Tanir Ozcelebi. Courtesy of Prof. Dr. Johan Lukkien. System Architecture and Networking Group Operating Systems (2INC0) 20/19 Introduction (01) Dr. Courtesy of Prof. Dr. Johan Lukkien System Architecture and Networking Group Course Overview Introduction to operating systems Processes, threads and

More information

Design Document. May Logging DC Wattmeter. Team Member: Advisor : Ailing Mei. Collin Christy. Andrew Kom. Client: Chongli Cai

Design Document. May Logging DC Wattmeter. Team Member: Advisor : Ailing Mei. Collin Christy. Andrew Kom. Client: Chongli Cai Design Document May13-06 Logging DC Wattmeter Team Member: Ailing Mei Andrew Kom Chongli Cai David Hoffman Advisor : Collin Christy Client: Garmin International Qiaoya Cui 0 Table of Contents EXECUTIVE

More information

RE for Embedded Systems - Part 1

RE for Embedded Systems - Part 1 REQUIREMENTS ENGINEERING LECTURE 2017/2018 Dr. Jörg Dörr RE for Embedded Systems - Part 1 Fraunhofer IESE Lecture Outline Embedded systems and their characteristics Requirements specifications (for embedded

More information

Topics: Memory Management (SGG, Chapter 08) 8.1, 8.2, 8.3, 8.5, 8.6 CS 3733 Operating Systems

Topics: Memory Management (SGG, Chapter 08) 8.1, 8.2, 8.3, 8.5, 8.6 CS 3733 Operating Systems Topics: Memory Management (SGG, Chapter 08) 8.1, 8.2, 8.3, 8.5, 8.6 CS 3733 Operating Systems Instructor: Dr. Turgay Korkmaz Department Computer Science The University of Texas at San Antonio Office: NPB

More information

DIOGENE (Digital I/O GENerator Engine) Project Requirements

DIOGENE (Digital I/O GENerator Engine) Project Requirements SCO-DIOGENE-0-- 1 of 13 DIOGENE (Digital I/O GENerator Engine) Project Requirements Document : SCO-DIOGENE-0-.doc Revision : SCO-DIOGENE-0-- 2 of 13 APPROVAL Name Signature Date Prepared by Sergio Cigoli

More information

How to use the IP generator from Xilinx to instantiate IP cores

How to use the IP generator from Xilinx to instantiate IP cores ÁÌ ¹ ÁÒØÖÓ ÙØ ÓÒ ØÓ ËØÖÙØÙÖ ÎÄËÁ Ò ÐÐ ¾¼½ µ ÓÙÖ ÔÖÓ Ø Úº½º¼º¼ 1 Introduction This document describes the course projects provided in EITF35 Introduction to Structured VLSI Design conducted at EIT, LTH.

More information

ITC213: STRUCTURED PROGRAMMING. Bhaskar Shrestha National College of Computer Studies Tribhuvan University

ITC213: STRUCTURED PROGRAMMING. Bhaskar Shrestha National College of Computer Studies Tribhuvan University ITC213: STRUCTURED PROGRAMMING Bhaskar Shrestha National College of Computer Studies Tribhuvan University Lecture 03: Program Development Life Cycle Readings: Not Covered in Textbook Program Development

More information

Embedded computing system

Embedded computing system Unit-1 EMBEDDED COMPUTING SYSTEM 1.1 COMPLEX SYSTEMS AND MICROPROCESSORS Embedded computer system is any device that includes a programmable computer but is not itself intended to be a general-purpose

More information

EE382V: System-on-a-Chip (SoC) Design

EE382V: System-on-a-Chip (SoC) Design EE382V: System-on-a-Chip (SoC) Design Lecture 8 HW/SW Co-Design Sources: Prof. Margarida Jacome, UT Austin Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu

More information

Chapter 8: Main Memory

Chapter 8: Main Memory Chapter 8: Main Memory Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Paging Structure of the Page Table Segmentation Example: The Intel Pentium 8.2 Silberschatz, Galvin

More information

Top Down Design. 2. Design Methodology

Top Down Design. 2. Design Methodology Top Down Design 1 A solution method where the problem is broken down into smaller subproblems, which in turn are broken down into smaller problems until each subproblem can be solved in a few steps. (Also

More information

Unit 2. Computer Control. PIC stands for PROGRAMMABLE INTERFACE CONTROLLER. A PIC chip takes in input signals and then controls output transducers

Unit 2. Computer Control. PIC stands for PROGRAMMABLE INTERFACE CONTROLLER. A PIC chip takes in input signals and then controls output transducers Unit 2 Computer Control PIC stands for PROGRAMMABLE INTERFACE CONTROLLER A PIC chip takes in input signals and then controls output transducers Name: Form: 2 ASIC or Application Specific Integrated Circuits

More information

C++ Programming Language Lecture 2 Problem Analysis and Solution Representation

C++ Programming Language Lecture 2 Problem Analysis and Solution Representation C++ Programming Language Lecture 2 Problem Analysis and Solution Representation By Ghada Al-Mashaqbeh The Hashemite University Computer Engineering Department Program Development Cycle Program development

More information

Introduction to PowerPoint 2010

Introduction to PowerPoint 2010 Introduction to PowerPoint 2010 PowerPoint is a system in the Microsoft Office Suite that enables you to present information in office meetings, lectures and seminars to create maximum impact in a minimal

More information

Chapter 9: Memory Management. Background

Chapter 9: Memory Management. Background 1 Chapter 9: Memory Management Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging 9.1 Background Program must be brought into memory and placed within a process for

More information

Internal Buffer/Boiler Module HZS 534

Internal Buffer/Boiler Module HZS 534 INTERNAL BUFFER/BOILER MODULE HZS 534 Internal Buffer/Boiler Module HZS 534 30.11.2015 Page 1 INTERNAL BUFFER-/BOILERMODUL HZS 534 Configuration HZS 534 internal buffer/boiler module for the heating controller

More information

Component Design. Systems Engineering BSc Course. Budapest University of Technology and Economics Department of Measurement and Information Systems

Component Design. Systems Engineering BSc Course. Budapest University of Technology and Economics Department of Measurement and Information Systems Component Design Systems Engineering BSc Course Budapest University of Technology and Economics Department of Measurement and Information Systems Traceability Platform-based systems design Verification

More information

Computer Hardware Requirements for Real-Time Applications

Computer Hardware Requirements for Real-Time Applications Lecture (4) Computer Hardware Requirements for Real-Time Applications Prof. Kasim M. Al-Aubidy Computer Engineering Department Philadelphia University Real-Time Systems, Prof. Kasim Al-Aubidy 1 Lecture

More information

Outline. policies. with some potential answers... MCS 260 Lecture 19 Introduction to Computer Science Jan Verschelde, 24 February 2016

Outline. policies. with some potential answers... MCS 260 Lecture 19 Introduction to Computer Science Jan Verschelde, 24 February 2016 Outline 1 midterm exam on Friday 26 February 2016 policies 2 questions with some potential answers... MCS 260 Lecture 19 Introduction to Computer Science Jan Verschelde, 24 February 2016 Intro to Computer

More information

Question Bank Microprocessor and Microcontroller

Question Bank Microprocessor and Microcontroller QUESTION BANK - 2 PART A 1. What is cycle stealing? (K1-CO3) During any given bus cycle, one of the system components connected to the system bus is given control of the bus. This component is said to

More information

CPS104 Computer Organization Lecture 1. CPS104: Computer Organization. Meat of the Course. Robert Wagner

CPS104 Computer Organization Lecture 1. CPS104: Computer Organization. Meat of the Course. Robert Wagner CPS104 Computer Organization Lecture 1 Robert Wagner Slides available on: http://www.cs.duke.edu/~raw/cps104/lectures 1 CPS104: Computer Organization Instructor: Robert Wagner Office: LSRC D336, 660-6536

More information

Ultra Low Power Microcontroller - Design Criteria - June 2017

Ultra Low Power Microcontroller - Design Criteria - June 2017 Ultra Low Power Microcontroller - Design Criteria - June 2017 Agenda 1. Low power technology features 2. Intelligent Clock Generator 3. Short wake-up times 4. Intelligent memory access 5. Use case scenario

More information

Example Project Report March 5, Table Of Contents. This is an outline of the content of your model identifying each piece:

Example Project Report March 5, Table Of Contents. This is an outline of the content of your model identifying each piece: Example Project Report March 5, 2014 Table Of Contents The Telegram Problem Description... 2 Class Diagrams... 3 Class Detail... 4 Class Blank... 4 Class Buffer... 4 Association Note... 4 Class... 5 Class

More information

Fredrick M. Cady. Assembly and С Programming forthefreescalehcs12 Microcontroller. шт.

Fredrick M. Cady. Assembly and С Programming forthefreescalehcs12 Microcontroller. шт. SECOND шт. Assembly and С Programming forthefreescalehcs12 Microcontroller Fredrick M. Cady Department of Electrical and Computer Engineering Montana State University New York Oxford Oxford University

More information

CSE 466 Software for Embedded Systems. CSE 466 Software for Embedded Systems

CSE 466 Software for Embedded Systems. CSE 466 Software for Embedded Systems CSE 466 Software for Embedded Systems Instructor: Gaetano Borriello CSE 572, Hours: by app t gaetano@cs.washington.edu Teaching Assistants: Brain French CSE 003, Hours TTh 2:30-5:30 bmf@cs.washington.edu

More information

INSTRUCTION MANUAL CONTAINS: MOUNTING DIMENSION: For RVs,Caravans,and boats METER for duo-battery charging solar controller,

INSTRUCTION MANUAL CONTAINS: MOUNTING DIMENSION: For RVs,Caravans,and boats METER for duo-battery charging solar controller, INSTRUCTION MANUAL ---------- METER for duo-battery charging solar controller, For RVs,Caravans,and boats ----------EPIPDB-COM series CONTAINS: Wall mounting board, can be mounted in or on the wall. With

More information

CPS104 Computer Organization Lecture 1

CPS104 Computer Organization Lecture 1 CPS104 Computer Organization Lecture 1 Robert Wagner Slides available on: http://www.cs.duke.edu/~raw/cps104/lectures 1 CPS104: Computer Organization Instructor: Robert Wagner Office: LSRC D336, 660-6536

More information

EE 109 Unit 12 Computer Organization

EE 109 Unit 12 Computer Organization 1 EE 19 Unit 12 Computer Organization 2 Review of some key concepts from the first half of the semester A BRIEF SUMMARY 3 A Few Big Ideas 1 Setting and clearing bits in a register tells the hardware what

More information

EE 109 Unit 12 Computer Organization. A Few Big Ideas 1. A Few Big Ideas 2 A BRIEF SUMMARY. Clocking or enables are necessary to say

EE 109 Unit 12 Computer Organization. A Few Big Ideas 1. A Few Big Ideas 2 A BRIEF SUMMARY. Clocking or enables are necessary to say EE 9 Unit Computer Organization Review of some key concepts from the first half of the semester and revisit what CECS prepares you to do in the future. A BRIEF SUMMARY A Few Big Ideas bits in a register

More information

ME 365 EXPERIMENT 3 INTRODUCTION TO LABVIEW

ME 365 EXPERIMENT 3 INTRODUCTION TO LABVIEW ME 365 EXPERIMENT 3 INTRODUCTION TO LABVIEW Objectives: The goal of this exercise is to introduce the Laboratory Virtual Instrument Engineering Workbench, or LabVIEW software. LabVIEW is the primary software

More information

Method & Tools for Program Analysis & Design

Method & Tools for Program Analysis & Design Method & Tools for Program Analysis & Design TMB208 Pemrograman Teknik Kredit: 3 (2-3) 1 Programming Logic and Design, Introductory, Fourth Edition 2 1 Programming Methods Based on structures of programming

More information

Chapter 1 - An Introduction to Computers and Problem Solving

Chapter 1 - An Introduction to Computers and Problem Solving Chapter 1 - An Introduction to Computers and Problem Solving 1.1 An Introduction to Computers 1.2 Windows, Folders, and Files 1.3 Program Development Cycle 1.4 Programming Tools 1 1.1 An Introduction to

More information

CSE 373 Final Exam 3/14/06 Sample Solution

CSE 373 Final Exam 3/14/06 Sample Solution Question 1. (6 points) A priority queue is a data structure that supports storing a set of values, each of which has an associated key. Each key-value pair is an entry in the priority queue. The basic

More information

I.-C. Lin, Assistant Professor. Textbook: Operating System Principles 7ed CHAPTER 8: MEMORY

I.-C. Lin, Assistant Professor. Textbook: Operating System Principles 7ed CHAPTER 8: MEMORY I.-C. Lin, Assistant Professor. Textbook: Operating System Principles 7ed CHAPTER 8: MEMORY MANAGEMENT Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Paging Structure of

More information

By the end of Class. Outline. Homework 5. C8051F020 Block Diagram (pg 18) Pseudo-code for Lab 1-2 due as part of prelab

By the end of Class. Outline. Homework 5. C8051F020 Block Diagram (pg 18) Pseudo-code for Lab 1-2 due as part of prelab By the end of Class Pseudo-code for Lab 1-2 due as part of prelab Homework #5 on website due before next class Outline Introduce Lab 1-2 Counting Timers on C8051 Interrupts Laboratory Worksheet #05 Copy

More information

FIFTH SEMESTER DIPLOMA EXAMINATION IN ENGINEERING/ TECHNOLOGY-MARCH 2014 EMBEDDED SYSTEMS (Common for CT,CM) [Time: 3 hours] (Maximum marks : 100)

FIFTH SEMESTER DIPLOMA EXAMINATION IN ENGINEERING/ TECHNOLOGY-MARCH 2014 EMBEDDED SYSTEMS (Common for CT,CM) [Time: 3 hours] (Maximum marks : 100) (Revision-10) FIFTH SEMESTER DIPLOMA EXAMINATION IN ENGINEERING/ TECHNOLOGY-MARCH 2014 EMBEDDED SYSTEMS (Common for CT,CM) [Time: 3 hours] (Maximum marks : 100) PART-A (Maximum marks : 10) I. Answer all

More information

THE DESIGN ENVIRONMENT FOR HETEROGENEOUS SYSTEMS

THE DESIGN ENVIRONMENT FOR HETEROGENEOUS SYSTEMS THE DESIGN ENVIRONMENT FOR HETEROGENEOUS SYSTEMS SystemC / SystemC AMS based Simulation and Modeling Technologies Outline COSIDE Today COSIDE 2.0 COSIDE Future 2 Management Summary Combination of analog

More information

Programmable Logic Controller

Programmable Logic Controller QEC25689 In modern century in this time more and more company which technological to use, so that everything become accurate and quicker. Along go forward technological and to the number of appliance of

More information

Module 1: Crash Prevention Lesson 3: Weather Information systems Programming Activity Using Arduino Teacher Resource Grade 6-8 Time Required

Module 1: Crash Prevention Lesson 3: Weather Information systems Programming Activity Using Arduino Teacher Resource Grade 6-8 Time Required Module 1: Crash Prevention Lesson 3: Weather Information systems Programming Activity Using Arduino Teacher Resource Grade 6-8 Time Required Weather Information Systems is a 120 minute lesson plan (90

More information

Hardware-Software Codesign. 1. Introduction

Hardware-Software Codesign. 1. Introduction Hardware-Software Codesign 1. Introduction Lothar Thiele 1-1 Contents What is an Embedded System? Levels of Abstraction in Electronic System Design Typical Design Flow of Hardware-Software Systems 1-2

More information

CPU ARCHITECTURE. QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system.

CPU ARCHITECTURE. QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system. CPU ARCHITECTURE QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system. ANSWER 1 Data Bus Width the width of the data bus determines the number

More information

I.-C. Lin, Assistant Professor. Textbook: Operating System Concepts 8ed CHAPTER 8: MEMORY

I.-C. Lin, Assistant Professor. Textbook: Operating System Concepts 8ed CHAPTER 8: MEMORY I.-C. Lin, Assistant Professor. Textbook: Operating System Concepts 8ed CHAPTER 8: MEMORY MANAGEMENT Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Paging Structure of the

More information

The Embedded computing platform. Four-cycle handshake. Bus protocol. Typical bus signals. Four-cycle example. CPU bus.

The Embedded computing platform. Four-cycle handshake. Bus protocol. Typical bus signals. Four-cycle example. CPU bus. The Embedded computing platform CPU bus. Memory. I/O devices. CPU bus Connects CPU to: memory; devices. Protocol controls communication between entities. Bus protocol Determines who gets to use the bus

More information

Process and data flow modeling

Process and data flow modeling Process and data flow modeling Vince Molnár Informatikai Rendszertervezés BMEVIMIAC01 Budapest University of Technology and Economics Fault Tolerant Systems Research Group Budapest University of Technology

More information

705 INSTALLATION MANUAL

705 INSTALLATION MANUAL 705 INSTALLATION MANUAL 2 Table of Contents Features...03 Specifications...04 Quick - Start...05 Remote Control...07 Hardware Installation...10 705 Models Additional Info...14 Owner s Record...15 3 Features

More information

Main Memory. Electrical and Computer Engineering Stephen Kim ECE/IUPUI RTOS & APPS 1

Main Memory. Electrical and Computer Engineering Stephen Kim ECE/IUPUI RTOS & APPS 1 Main Memory Electrical and Computer Engineering Stephen Kim (dskim@iupui.edu) ECE/IUPUI RTOS & APPS 1 Main Memory Background Swapping Contiguous allocation Paging Segmentation Segmentation with paging

More information

13-1 Memory and Caches

13-1 Memory and Caches 13-1 Memory and Caches 13-1 See also cache study guide. Contents Supplement to material in section 5.2. Includes notation presented in class. 13-1 EE 4720 Lecture Transparency. Formatted 13:15, 9 December

More information

UNIVERSITY OF CALIFORNIA, SANTA CRUZ BOARD OF STUDIES IN COMPUTER ENGINEERING CMPE13/L: INTRODUCTION TO PROGRAMMING IN C SPRING 2013

UNIVERSITY OF CALIFORNIA, SANTA CRUZ BOARD OF STUDIES IN COMPUTER ENGINEERING CMPE13/L: INTRODUCTION TO PROGRAMMING IN C SPRING 2013 Introduction Reading Concepts UNIVERSITY OF CALIFORNIA, SANTA CRUZ BOARD OF STUDIES IN COMPUTER ENGINEERING CMPE13/L: INTRODUCTION TO PROGRAMMING IN C SPRING 2013 Lab 2 Bouncing LEDs In this lab, you will

More information

12.1. Unit 12. Exceptions & Interrupts

12.1. Unit 12. Exceptions & Interrupts 12.1 Unit 12 Exceptions & Interrupts 12.2 Disclaimer 1 This is just an introduction to the topic of interrupts. You are not meant to master these right now but just start to use them We will cover more

More information

Part 2: Principles for a System-Level Design Methodology

Part 2: Principles for a System-Level Design Methodology Part 2: Principles for a System-Level Design Methodology Separation of Concerns: Function versus Architecture Platform-based Design 1 Design Effort vs. System Design Value Function Level of Abstraction

More information

Chapter 4 NETWORK HARDWARE

Chapter 4 NETWORK HARDWARE Chapter 4 NETWORK HARDWARE 1 Network Devices As Organizations grow, so do their networks Growth in number of users Geographical Growth Network Devices : Are products used to expand or connect networks.

More information

Lecture 01: Basic Structure of Computers

Lecture 01: Basic Structure of Computers CSCI2510 Computer Organization Lecture 01: Basic Structure of Computers Ming-Chang YANG mcyang@cse.cuhk.edu.hk Reading: Chap. 1.1~1.3 Outline Computer: Tools for the Information Age Basic Functional Units

More information

System Reset with Delay Time Circuit Monolithic IC PST596~598 Series

System Reset with Delay Time Circuit Monolithic IC PST596~598 Series System Reset with Delay Time Circuit Monolithic IC 96~98 Series July 21, 2000 Outline This IC functions in a variety of CPU systems and other logic systems, to detect supply voltage and reset the system

More information

Memory and multiprogramming

Memory and multiprogramming Memory and multiprogramming COMP342 27 Week 5 Dr Len Hamey Reading TW: Tanenbaum and Woodhull, Operating Systems, Third Edition, chapter 4. References (computer architecture): HP: Hennessy and Patterson

More information

Chapter 8: Main Memory

Chapter 8: Main Memory Chapter 8: Main Memory Operating System Concepts 8 th Edition,! Silberschatz, Galvin and Gagne 2009! Chapter 8: Memory Management Background" Swapping " Contiguous Memory Allocation" Paging" Structure

More information

Agenda. Peer Instruction Question 1. Peer Instruction Answer 1. Peer Instruction Question 2 6/22/2011

Agenda. Peer Instruction Question 1. Peer Instruction Answer 1. Peer Instruction Question 2 6/22/2011 CS 61C: Great Ideas in Computer Architecture (Machine Structures) Introduction to C (Part II) Instructors: Randy H. Katz David A. Patterson http://inst.eecs.berkeley.edu/~cs61c/sp11 Spring 2011 -- Lecture

More information

WS_CCESBF7-OUT-v1.00.doc Page 1 of 8

WS_CCESBF7-OUT-v1.00.doc Page 1 of 8 Course Name: Course Code: Course Description: System Development with CrossCore Embedded Studio (CCES) and the ADSP-BF70x Blackfin Processor Family WS_CCESBF7 This is a practical and interactive course

More information

Last 2 Classes: Introduction to Operating Systems & C++ tutorial. Today: OS and Computer Architecture

Last 2 Classes: Introduction to Operating Systems & C++ tutorial. Today: OS and Computer Architecture Last 2 Classes: Introduction to Operating Systems & C++ tutorial User apps OS Virtual machine interface hardware physical machine interface An operating system is the interface between the user and the

More information

Blackfin Optimizations for Performance and Power Consumption

Blackfin Optimizations for Performance and Power Consumption The World Leader in High Performance Signal Processing Solutions Blackfin Optimizations for Performance and Power Consumption Presented by: Merril Weiner Senior DSP Engineer About This Module This module

More information

Platform-based Design

Platform-based Design Platform-based Design The New System Design Paradigm IEEE1394 Software Content CPU Core DSP Core Glue Logic Memory Hardware BlueTooth I/O Block-Based Design Memory Orthogonalization of concerns: the separation

More information

Memory Management. Contents: Memory Management. How to generate code? Background

Memory Management. Contents: Memory Management. How to generate code? Background TDIU11 Operating systems Contents: Memory Management Memory Management [SGG7/8/9] Chapter 8 Background Relocation Dynamic loading and linking Swapping Contiguous Allocation Paging Segmentation Copyright

More information

Chapter 12. UML and Patterns. Copyright 2008 Pearson Addison-Wesley. All rights reserved

Chapter 12. UML and Patterns. Copyright 2008 Pearson Addison-Wesley. All rights reserved Chapter 12 UML and Patterns Copyright 2008 Pearson Addison-Wesley. All rights reserved Introduction to UML and Patterns UML and patterns are two software design tools that can be used within the context

More information

EEL 4783: Hardware/Software Co-design with FPGAs

EEL 4783: Hardware/Software Co-design with FPGAs EEL 4783: Hardware/Software Co-design with FPGAs Lecture 5: Digital Camera: Software Implementation* Prof. Mingjie Lin * Some slides based on ISU CPrE 588 1 Design Determine system s architecture Processors

More information