THE DESIGN ENVIRONMENT FOR HETEROGENEOUS SYSTEMS
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1 THE DESIGN ENVIRONMENT FOR HETEROGENEOUS SYSTEMS SystemC / SystemC AMS based Simulation and Modeling Technologies
2 Outline COSIDE Today COSIDE 2.0 COSIDE Future 2
3 Management Summary Combination of analog and mixed-signal hardware and software Integration of standard tools (Matlab, Cadence, Synopsys, etc.) HiL simulation, testing Large libraries Improved and extended analog solvers Generation of IP-protected customer models Formal verification 3
4 SystemC AMS Language Principal and Base for COSIDE C++ based Hardware description language for higher abstraction levels Hosted and standardized by the Accellera Systems Initiative (former OSCI) SystemC focuses on the description of digital hard- and software on higher abstraction levels SystemC AMS extends SystemC for abstract modeling of analog/mixedsignal 4
5 Modeling language comparison Level of Abstraction MAST (A) Spice (A) Modelica * (A) VHDL-AMS * Verilog-AMS * Verilog-A * (A) SystemC-AMS SPICE (A) Fast Spice (A) Ptolemy SPW (A/D) SystemC/TLM SystemC-AMS* Simulation Speed SystemVerilog * (D) (A/D) VHDL * (Verilog) * (D) * Std. Language (A) mainly analog focused (D) mainly digital focused (A/D) mixed signal focus 5
6 SystemC AMS Based System Modeling The basic technology for the Accellera SystemC AMS language standard was developed by Fraunhofer IIS/EAS Modeling method / language Fast-Spice Simulator Computing time for 1 sec real time sec approx. 30 years VHDL/VHDL-AMS sec approx. 1 day SystemC / SystemC AMS 5 sec (Source: Dr. Georg Pelz Infineon AG; Simulation of a window lifter) Advantage: SystemC/SystemC AMS modeling technology enables the overall system simulation of application scenarios Downside: Technology is complex und modeling effort is high 6
7 COSIDE Design Environment based on SystemC / SystemC AMS Powerful Modeling Modelling Capabilities Schematic Design Entry Accellera System Initiative Compliant Full TLM 2.0 Support SystemC / VHDL Mixed Language Modeling Basic Model Libraries Profiling Performance and Memory Leakages, Model & TB Generation Designed by the Developers of the SystemC AMS Proof-of-Concept Library 7
8 COSIDE Customer Advantages Improved modelling efficiency Higher model quality Low entry level Improved maintainability Enabling model reuse Extended model (re)use cases License-free simulation 8
9 COSIDE Schematic Editor Schematic Editor Eclipse integrated (GMF/GEF based) Double click to source file, hierarchy browsing Autorouting also if modules moved Improved parameter handling Advanced editing features Advanced Copy&Paste Printing and svg, png, export 9
10 COSIDE TLM Modeling Support Full TLM 2.0 Support Additional TLM generic library (full TLM 2.0 compliant) 10
11 COSIDE XML-Editor Frontend / Code completion Easy model definition via XML editor frontend SC/SCA Syntax highlighting Code completion with suggestions 11
12 COSIDE Simulation Control, Debugging Simulation Control, Debugging SCSimCtrl: Advanced Drag n Drop Trace Selection, Hierarchy Browsing and and Simulation Control Debugging Facilities in in Stand-alone as as well as as in in Coupled Simulation Scenarios 12
13 COSIDE Easy Tool Coupling Tool Couplings for model exchange and implementation level verification Customer Model Generation with ensured IP-Protection Model Exchange with reproducible analogue simulation behavior Hardware in the Loop Simulation with dspace, ZedBoard (ARM ) 13
14 COSIDE Direct SystemC AMS HiL-Simulation Test of Component Specification (e.g. for IC s) Test of Hardware Components in a not yet existing environment SystemC AMS Model ds1006.x86 Source: dspace 14
15 COSIDE SystemC HiL-Testing with download monitor integrate Source: ZedBoard.org Setup SystemC UVM high level Regression Tests reuse Testbench for Prototype Validation in the Laboratory Integrate Lab. Equipment via RS232, GPIB etc. 15
16 COSIDE State Chart Editor UML based State Chart design entry Code generation backend 16
17 COSIDE State Chart Code generation Statechart Code Generator hierarchic statechart back annotation XML Java/XSLT complex operations: design rule checks, automated verification, model transformations, e.g. remove complex structures, hierarchy flatten, preprocessing, target specific backend: Java/XSLT Java/XSLT Java/XSLT simplified statechart SystemC behavioral Controller C-code NuSMV counter examples 17
18 COSIDE Formal Verification of State Charts Back Annotation Formal Checker 18
19 COSIDE SystemC AMS Libraries Library with approx. 130 basic elements Optimized Line models Failure Injection Statistical Simulation Regression Test Concept Architecture Select Signal bundles / Abstract signals / Reconnect signals from test bench Tracing and Object access via pattern matching Easily usable TLM Library with debug feature 19
20 COSIDE
21 COSIDE Highlights Eclipse 4 based New Model libraries Completely SystemC AMS 2.0 compliant Model templates Documentation Example Projects Improved usability Screen casts for typical use cases 21
22 COSIDE Piece Wise Linear (PWL) SystemC AMS Extension Fast and robust modelling of diodes Modelling of switched networks, pwm stages, Modelling of slew rates 22
23 COSIDE SystemC / SystemC AMS Spice Integration Mixing Spice and SystemC-AMS ELN modules Spice linked to SystemC-AMS kernel SystemC-AMS Spice modules or embedded Spice description (subcircuits) and modelcards 23
24 COSIDE RF SystemC / SystemC AMS Libraries RF modelling at system level Library of basic elements 24
25 COSIDE Mechanical SystemC AMS Library Fast and robust models Basics for modelling mechanical environments 25
26 Library Licensing Pre-compiled inside larger models, distribution always allowed Apache source code available COSIDE Open License Source code available distribution is allowed pre-compiled only COSIDE License no source code available 26
27 Library Model Import Green and yellow signed models can be imported into the current project They can be renamed and adopted They can used as templates for own primitive models 27
28 Library Documentation Short description preview Direct access via menu Completely re-worked and improved 28
29 Example Projects Examples with typical use cases and modelling techniques Import into current workspace Models or libraries can be used as templates via copy model / library function 29
30 Documentation PDF based documentation Completely re-worked and re-structured 30
31 Screen Casts 31
32 COSIDE Test and Build Flow 32
33 COSIDE - Future System level tool-suite for modelling, design, verification and integration of HW/SW mixed signal systems 33
34 COSIDE - Future Verification UVM-SystemC (AMS) integration Model Libraries Documentation / Usability Cooperation with partners Your requests 34
35 THANK YOU FOR YOUR ATTENTION YOUR CONTACT Karsten Einwich Group Manager Thomas Hartung Marketing / Sales COSIDE thomas.hartung@eas.iis.fraunhofer.de Fraunhofer Institute for Integrated Circuits IIS Design Automation Division EAS Zeunerstraße Dresden, Germany 35
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