Digital Integrated Circuits

Transcription

1 Digital Integrated Circuits EE141 Fall 2005 Tu & Th 11-12: McLaughlin What is This Class About? Introduction to Digital Integrated Circuits Introduction: Issues in digital design CMOS devices and manufacturing technology The CMOS inverter Combinational logic structures Propagation delay, noise margins, power Sequential logic gates; timing Arithmetic building blocks Interconnect: R, L and C Memories and array structures Design methods EE141 2

2 What will You Learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: Power dissipation Speed Reliability EE141 3 Interludium: Administrativia Instructor TAs Ke Lu Discussion + lab kelu@berkeley.edu Office Hours: TBD Dejan Markovic dejan@eecs.berkeley.edu Office hours: 511 Cory Wed 10:00-12:00pm Lynn Wang Discussion + lab ting0918@eecs.berkeley.edu Office Hours: TBD Reader TBD EE141 4

3 The Web-Site The sole source of information Class and lecture notes Assignments and solutions Lab and project information Exams Many other goodies Save a tree! EE141 5 Class Admission The class is over-enrolled! 72 enrolled, 30 waitlisted, 60 rejected Waitlist priority Graduating seniors Grad students (prelim) Other grad students, Juniors We can accommodate ~75 students Make sure your name is on the class roll! EE141 6

4 Discussions and Labs Discussion sessions Mo 1-2pm, 203 McLaughlin Mo 5-6pm, 293 Cory Pick any of the two (they are covering the same material) Labs (353 Cory) Mo 3-6pm Tu 3:30-6:30pm class poll: move to Wed? Th 3:30-6:30pm Pick the one that fits you the best (pending availability) and STICK TO IT! EE141 7 Your EE141 Week at a Glance Mon Tue Lec (Dejan) 203 McLaughlin DISC* (Ke) 203 McLaughlin OH (TA1) TBD Lab (Ke) 353 Cory DISC* (Lynn) 293 Cory Lab (Lynn/Ke) 353 Cory Wed Thu Fri Problem Sets Due OH (Dejan) 511 Cory Lec (Dejan) 203 McLaughlin TA mtng OH (TA2) TBD? Lab (Lynn) 353 Cory * Discussion sessions will cover identical material EE141 8

5 Class Organization 9 homework assignments 2 design projects Labs: 5 software, 1 hardware Exams: 2 midterms, final Midterm 1: Th October 6, 6:30-8:00pm Midterm 2: Th November 10, 6:30-8:00pm Final: Th December 15, 5-8pm EE141 9 Grading Policy Homeworks: 10% Labs: 10% Projects: 20% Midterms: 30% Final: 30% EE141 10

6 Class Material Textbook: Digital Integrated Circuits: A Design Perspective, by J. Rabaey, A. Chandrakasan, B. Nikolic, 2 nd Edition, (Prentice Hall 2002) Lab manuals Available on the web-page Check web-page for the availability of tools EE Software Cadence software only! Phased out the Micromagic software Online documentation and tutorials HSPICE and IRSIM for simulation EE141 12

7 Getting Started Assignment 1: Getting SPICE to work see web-page also The SPICE Book, by A. Vladimirescu No discussion sessions or labs this week First discussion sessions in Week 2 First software lab in Week 3 EE EE141 Fall 2005 Lecture 1 Introduction

8 Introduction Why is designing digital ICs different today than it was before? Will it change in the future? EE The First Computer (1832) The Babbage Difference Engine 25,000 parts cost: 17,470 EE141 16

9 ENIAC The First Electronic Computer (1946) EE The Transistor Revolution First transistor Bell Labs (1948) EE141 18

10 The First Integrated Circuits Bipolar logic (1960 s) ECL 3-input Gate Motorola (1966) EE Intel 4004 Microprocessor (1971) 2,300 transistors (12mm 2 ) 108 KHz operation (10µm) EE141 20

11 Evolution in Transistor Count EE Intel Pentium 4 Microprocessor Intel (2000) 42 M transistors (217mm 2 ) 1.5 GHz operation (0.18µm) EE141 22

12 What Happened over 30 Years? ,300 transistors 108 KHz operation ~15,000 x 42 M transistors 1.5 GHz operation Comparison (automotive): Travel from San Francisco to New York in 13 sec! EE Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months He made a prediction that semiconductor industry will double its effectiveness every 18 months EE141 24

13 Moore s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION Source: Electronics, April 19, EE Evolution in Complexity EE141 26

14 Microprocessor Examples Moore s Law Number of transistors Logic density Die size Frequency Power EE Moore s Law in Microprocessors Transistors (MT) X growth in 1.96 years! Pentium 4 Pentium Pro (P6) Pentium (P5) 486 (P4) 386 (P3) 286 (P2) (P1) Year Source: S. Borkar (Intel) Transistors on Lead Microprocessors double every 2 years EE141 28

15 Moore s Law Logic Density 1000 Logic Transistors/mm 2 Logic Density i860 Pentium II (R) 486 Pentium Pro (R) Pentium (R) 2x trend Source: Intel 1.5µ 1.0µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Shrinks and compactions meet density goals New micro-architectures drop density EE Die Size Growth 100 Die size (mm) Pentium Pro 486 Pentium ~7% growth per year ~2X growth in 10 years Year Source: S. Borkar (Intel) Die size grows by 14% to satisfy Moore s Law EE141 30

16 Frequency Frequency (Mhz) Doubles every 2 years Pentium 4 Pentium Pro Pentium Year Source: S. Borkar (Intel) Lead Microprocessor frequency doubles every 2 years EE Processor Frequency Trend 10,000 Intel IBM Power PC DEC Gate delays/clock Processor freq scales by 2X per generation 100 Mhz 1, S 21164A A Pentium(R) II MPC Pentium Pro 601, 603 (R) Pentium(R) 10 Gate Delays/ Clock Source: V. De, S. Borkar ISLPED 99 Frequency doubles each generation Number of gates/clock reduce by 25% EE141 32

17 Power 100 Power (Watts) Pentium Pro Pentium Year Source: S. Borkar (Intel) Lead Microprocessor power continues to increase EE Processor Power 100 Max Power (Watts) Pentium II (R) Pentium Pro (R) Pentium(R) 486 Pentium(R) MMX? µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Source: Intel Lead processor power increases every generation Compactions provide higher performance at lower power EE141 34

18 Power will be a Problem Power (Watts) KW 5KW 1.5KW 500W Pentium Pro Pentium Year Source: S. Borkar (Intel) Power delivery and dissipation will be prohibitive EE Power Density will Increase Power Density (W/cm 2 ) Rocket Nozzle Nuclear Reactor 8086 Hot Plate Pentium Pro Pentium Year Source: S. Borkar (Intel) Power density too high to keep junctions at low Temp EE141 36

19 Power Delivery Challenges Icc (amp) 1, L(di/dt)/Vdd Pentium Pro Pentium Year 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E E+00 1.E E-02 1.E E-04 Pentium Pro Pentium Year Source: S. Borkar (Intel) High supply currents at low voltage: Challenges: IR drop and L(di/dt) noise EE Not Only Microprocessors Cell Phone Small Signal RF Power RF Digital Cellular Market (Phones Shipped) Power Management Year Analog Baseband Units (M) (703) (776) (836) (889) Sources: Gartner Dataquest, CTIA, Strategy Analytics Digital Baseband (DSP + MCU) EE141 38

20 Other Wireless Devices Computation Communication 30M TV 95% by 2006 PAN LAN WAN Cell Tx 700M 180,464,003 subscribers in US Throughput, Complexity, Power EE Productivity Trends 10,000,000 10,000 Complexity Logic Transistor per Chip(M) 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. 58%/Yr. compounded Complexity growth rate x x x x x x x Today x 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity EE141 40

21 Challenges in Digital Design DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock Distribution Everything looks a little different? 1/DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and there s a lot of them! EE Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE D n+ EE141 42

22 Why Scaling? Technology shrinks by 0.7 per generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x How to design chips with more and more functions? Design engineering population does not double every two years Need to understand different levels of abstraction EE Outlook Performance 2x / 16 months 1 T instructions/s GHz clock Complexity No of transistors: 1 Billion Die area: 40mm x 40mm Power 10kW! Leakage: 1/3 of total Power P. Gelsinger, µprocessors for the New Millennium, ISSCC 2001 EE141 44

23 Next Class Introduce basic metrics for design of integrated circuits how to measure delay, power etc. Brief intro to IC manufacturing and design EE141 45