New plasma processes for improved dimensional control and LWR for a 28nm gate patterning

Transcription

1 New plasma processes for improved dimensional control and LWR for a 28nm gate patterning Onintza Ros a, Erwine Pargon b, Sebatien Barnola c, Pascal Gouraud a, Marc Fouchier b a STMicroelectronics, 85 rue Jean Monnet, Crolles Cedex, France b LTM, UMR 5129, Université Grenoble Alpes ; CNRS, c CEA-Leti Minatec, 17 rue des Martyrs, F-3854 Grenoble Cedex.17 rue des Martyrs, 3854 Grenoble Cedex9, France

2 Issue description 2 L 1 L 2. Local OVL non-alignment of 11nm! L 1 >L 2 Planar deprocessing after full etch Design Local pattern distortion is observed after gate patterning.

3 Gate Etch Process Partitioning 3 Litho HBr Cure Trim SiARC Open SoC Open HM Open Full Etch PR PR PR SiARC SiARC SiARC SoC SoC SoC SoC SoC SoC Oxide HM POLY Oxide HM POLY Oxide HM POLY Oxide HM POLY Oxide HM POLY POLY Oxide POLY a) b) c) d) e) f) g) The cure step has been identified as a root cause for Gate Shifting

4 Pattern shifting 4 Cure step leads to polymer degradation and leads to an overall resist flowing. PR after lithography (5nm left) PR after HBr cure (45nm left) SEM Xsection (by LAM research) The resist reflow during HBr cure is responsible of gate shifting. Cure HBr New challenge Pattern shifting

5 Pattern Transfer SiARC etch without Cure 5 Cure step removal allows to maintain respectable Gate shifting but increases LWR Pictures after SiARC open Pitch 1 Pitch 2 With HBr Cure Low LWR~3.5nm High Gate Shift~4,5nm Without HBr Cure High LWR~11,8nm Low Gate shift ~,5nm A compromise have to be found to control both Gate shifting and LWR. We will focus over SiARC etching process and subsequent pattern transfer steps

6 Pitch = CD+Space a) b) c) Metrology issue 6 pitch1 pitch1 pitch2 pitch3 pitch2 pitch3 Pitch shift (nm) Pitch (nm) Pitch Shift (nm) pitch4 pitch4 Pitch 1 Pitch 2 Pitch 3 Pitch 4 Design Full Etch Pitch 4 remains stable after etch while Pitch 2 is increased. Pitch 2 shift is a signature of pattern shifting from initial design.

7 Two methods for LWR 7 CD-SEM Tilted AFM Xi 1 y 14µm y i Line i n LWR = 3 x stdev(cd) 45 LER = 3 x stdev(y) Top view observations LWR and LER Allows spectral analysis Only for LER Half profile scanning Estimation of LER all along the pattern height

8 Comparison of SiARC plasma etching processes 8 CF 4 condition SF 6 condition CD = 43nm PR Th = 99nm CD = 44,8nm PR Th = 78nm CD = 47nm PR Th = 4nm F/C A R XPS over Photoresist Surface Bulk A ngle ER (nm/s) PR SiARC At % XPS results over SiARC Ref C1s O1s Si2p F1s A C-rich surface layer in decreases PR ER and increases LWR. SiARC ER is higher in due O depletion by Carbon F-rich surface layer in increases PR ER and trims PR smoothing the surface.

9 Pattern Transfer SiARC etch without Cure 9 New process in was proved to improve Gate Shifting and LWR Pictures after SiARC open Pitch 1 Pitch 2 POR condition condition Gate Shifting (nm) GS in SiARC 6.5nm 1.3nm.5nm POR LWR (nm) LWR after SiARC open 11.8nm 4.8nm 3.5nm POR

10 Study of Roughness over Photoresist 1 CD-SEM Measures LER ~3.7nm LER ~12.5nm CF 4 condition Height (nm) Reference Reference PR SiARC LER (nm) LER PR 4.5nm 15.2nm 2.7nm LER SiARC - 1.9nm 2.8nm LER ~3.7nm SF 6 condition In photoresist LWR is degraded during process and partially transfered into SiARC. In, F rich surface layer will trim the photoresist and smooth it during transfer. Resulting LER is better in plasmas

11 Roughness transfer into Silicon 11 PSD (nm) 1 1 Spectral analysis after pattern transfer 1 SiARC Silicon Gate Shifting (nm) nm POR GS in Silicon 1.3nm.5nm LWR (nm) nm POR LWR in Silicon 6.3nm 5.1nm PSD (nm) 1 1 SiARC Silicon 1E Wavenumber (Kn, nm -1 ) After transfer to Silicon, plasma is the best option for LWR and GS decrease In all roughness frequencies are increased but during pattern transfer just low frequencies are transferred, leading to high LWR. Spectral analysis of LWR in does not show roughness improvements since lithography value is underestimated. Despite subsequent gate etch steps degrade LWR.

12 How to improve LWR? 12 Measures over Photoresist LWR = 4.9nm LWR = 4.1nm LWR = 3.7nm HBr Cure Trim GS 1.nm 6.nm 1.4nm LER 4.4nm 3.nm 2.2nm Photoresist trim has been identified as a good option to limit LWR without Gate Shifting. Litho Trim

13 Measures over SiARC LWR = 4.9nm Trim steps to correct LWR 13 LWR = 4.8nm LWR (nm) LWR measure over Silicon 5nm 4.5nm 4nm Std Process Trim- Gate Shift (nm) Gate Shifting measured over Silicon 6.6nm 85%.5nm 1nm Std Process Trim SF 6 LWR = 4.nm LWR measures taken over SiARC show a big roughness improvement with Trim step addition. Measures after transfer to Silicon prove that Gate shifting will not be degraded during gate etch but LWR can be degraded due to subsequent etch steps. Trim SF 6

14 Cure steps improve LWR but distort gate patterns. Cure step removal requires new plasma processing for gate patterning. Conclusion 14 A new SiARC etching process in has been compared to the standard process in SiARC etching in leads to C-rich hard surficial layers that increase LWR SiARC etching in leads to F-rich reactive layers triming photoresist and resulting in lower LWR. AFM gate profile analysis shows that LER is lower in SiARC than in Photoresist. Spectral analysis of LWR transfer for these two plasmas shows a degradation of LWR during gate etch processing. CF 4 condition 1 SF 6 condition Gate Shifting measured over Silicon Addition of Trim steps has been proved to reduce initial LWR New process Trim- allows GateShifting improvement of a 85% Gate Shift (nm) 8 6.6nm % 1nm.5nm Std Process Trim

15 Thank you for your attention

16 How to solve it? 16 Gateshiftinghas an impact on the electrical performance of the device. The cure stepismandatoryto ensureminimizedgatelwr but itisthe main contributorto pattern shifting. LITHO CURE Trim PR+SiARC New strategies have to be implemented to fulfill the requirements of the 2nm technological node in terms of LWR and gate shifting: 1. Optimization of the hard mask opening steps (Si ARC etching and trim, SOC and TEOS etching) 2. Optimization of the cure step SiARC wo CURE, wo TRIM

17 Study of Roughness over Photoresist 17 CF 4 condition Height (nm) Reference PR SiARC LER (nm) LER PR 4.5nm 15.2nm 2.7nm LER SiARC - 1.9nm 2.8nm SF 6 condition In initial PR roughness is partially transferred into SiARC sidewalls. In, initial PR roughness is smoothed during SiARC opening. Resulting LER is better in plasmas

18 Comparison of SiARC plasma etching processes 18 At (%) AR XPS Measures over photoresist F1s F1s Etch Rate (nm/s) At % CD = 43nm PR Th = 99nm CF 4 condition CD = 44,8nm PR Th = 78nm XPS & ER Measures over SiARC ERPR ERSiARC 7V 6V C1s O1s F1s SF 6 condition CD = 47nm PR Th = 4nm F/C Angle A C-rich hard surface layer is deposed in plasmas that prevents photoresist etching and increases LWR. In plasmas a F-rich surface layer increases photoresist etch rate and LWR is not impacted. SiARC ER is higher in due to a higher C and F content that will increase Oxygen depletion and Si Etch