SOI REQUIRES BETTER THAN IR-DROP. F. Clément, CTO
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1 SOI REQUIRES BETTER THAN IR-DROP F. Clément, CTO
2 Content IR Drop Vs. System-level Interferences CWS Expertise Accuracy and Performance Silicon Validation Conclusion Copyright CWS
3 Sensitive Block IR Drop Vs. System-level Interferences IR Drop tools address internal noise impact on digital blocks High immunity to noise (limited risk) Single power domain analysis No signal coupling analysis There is a need to evaluate external noise impact on sensitive blocks: System-level Interference High sensitivity to noise Multiple power domain analysis Sensitive Analog/RF signal lines are potential noise targets D 1 DAC + LPF D 2 MIXER CWS offers the only comprehensive solution to address system-level interference with performance and accuracy Copyright CWS
4 Content IR Drop Vs. System-level Interferences CWS Expertise Accuracy and Performance Silicon Validation Conclusion Copyright CWS
5 What is WaveIntegrity? Agressor Block A Design Analog Victim Block C WaveIntegrity models all the noise going through the system levels Interconnect Metal Stack Package Silicon Substrate WaveIntegrity offers a way to model the full system and to identify all electrical noise in a truely globlal way Agressor Block B PCB WaveIntegrity produces testbench annotations to evaluate the impact of noise on RF/analog victims Copyright CWS
6 WaveIntegrity: The Strengths Global Approach Analysis of noise propagated through combined interconnect, silicon substrate, package and PCB Noise aggression from, and impact on, any location from SOC, package or PCB Run-time & Capacity Full hierarchical modeling Frequency domain analysis with parallel processing Scalable with design complexity Copyright CWS
7 WaveIntegrity: The Added Values First System Integration Provides iteratively an accurate prediction of system noise Assists designer in making educated architectural/design trade-off decisions Physical Implementation Fast run-time performance provides rapid feedback on each design change Simulation results complement designer s expertise to find best implementation Bidirectional communication between chip, package, board design groups, as well as with IP providers Iterations on Silicon Failures Allows designers to calibrate modeling tools to perfectly match silicon results Fix failures with higher efficiency and control the need for over-engineering Copyright CWS
8 Usage Examples SOC Integration Design: 40nm, 40um2, 20 million gates, QFN 64 pins + grounded exposed pad Digital noise black-boxes generated from Excel spreadsheet using CWS NoisePrototyper allowed early floorplanning. Chip leader, RF team, SOC implementation team, analog team. Added-value: Floorplan optimization, MiM cap sizing, design (digital + analog) optimization, packaging strategy qualification. Chippackageboard Integration Silicon Debugging Design: 28nm FD-SOI, 50um2, 200 million gates, BGA bumps SOC + package co-design team, PHYs design team Added-value: Packaging strategy qualification Design: 28nm FD-SOI USB design team Added-value: Packaging strategy qualification, validation of PHY integration specifications Design 55nm, 40um2, 5 million gates, QFN 128 pins with isolated exposed pad RF, digital and top implementation Added-value: Issues (seen in measurement) confirmation or explanation, counter-measure investigations Copyright CWS
9 Automotive Flow Integration and Apps Set-Top Boxes Ultra-wide-band RF tuners integration together with demodulation and error SMPS integration with low power designs Analog Design Flow Virtuoso, Pyxis FLOW INTEGRATION Digital Design Flow SOCEncounter TCL plugin WaveIntegrity SPICE Simulation Spectre, Eldo, AFS, Hspice Accurate conducted EMI simulation for automotive applications RF tuner integration for full CMOS car radios BluetoothLE integration with micro-controllers Biomedical Digital Simulation NCsim, Questa, ModelSim, VCS Parasitic Extraction Calibre, QRC MultiMedia Copyright CWS
10 Content IR Drop Vs. System-level Interferences CWS Expertise Accuracy and Performance Silicon Validation Conclusion Copyright CWS
11 Silicon Substrate Parasitics in Extraction Flow Example Measurement demonstrated a requirement to include silicon substrate parasitics when designing RF SOI devices Field solvers such as Momentum provide golden reference - Lack of integration in extraction flow leads to lengthy and cumbersome manual use CWS partnered with Mentor Graphics to deliver fast and easy-to-use solution while preserving accuracy - Field solver accuracy - 2 minutes impact on complete extraction+simulation flow - Push-button solution Copyright CWS
12 Experimental Context Simulation of silicon substrate impact on C off shunt on one RF switch branch 12 series of 7 parallel device with 12 fingers (Wtotal=1.75mm) Comparison of simulation results accounting for various parameters Silicon substrate port definition 12 ports one for each set of serial devices 84 ports one per device PEX extraction mode Resistance and capacitance Capacitance only Copyright CWS
13 Definition of Silicon Substrate Ports 12 Ports User assisted One for each row of parallel devices 84 ports Fully automated One for each device S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S1.1 S1.2 S1.3 S1.4 S1.5 S1.6 S1.7 S2.1 S2.2 S2.3 S2.4 S2.5 S2.6 S2.7 S3.1 S3.2 S3.3 S3.4 S3.5 S3.6 S3.7 S4.1 S4.2 S4.3 S4.4 S4.5 S4.6 S4.7 S5.1 S5.2 S5.3 S5.4 S5.5 S5.6 S5.7 S6.1 S6.2 S6.3 S6.4 S6.5 S6.6 S6.7 S7.1 S7.2 S7.3 S7.4 S7.5 S7.6 S7.7 S8.1 S8.2 S8.3 S8.4 S8.5 S8.6 S8.7 S9.1 S9.2 S9.3 S9.4 S9.5 S9.6 S9.7 S10.1 S10.2 S10.3 S10.4 S10.5 S10.6 S10.7 S11.1 S11.2 S11.3 S11.4 S11.5 S11.6 S11.7 S12.1 S12.2 S12.3 S12.4 S12.5 S12.6 S12.7 Copyright CWS
14 Momentum vs. SiPEX Comparison Interconnects Context Silicon Substrate Total run-time [sec] PLS size [MB] C off shunt [ff] 1 none ,6 2 R + C + CC ,3 3 R + C + CC 4 R + C + CC 5 R + C + CC 6 C + CC Momentum 12 ports SiPEX 12 ports SiPEX 84 ports SiPEX 12 ports 2303(*) 59,3 79, ,2 77, ,4 78, ,8 77,4 25% impact from silicon substrate parasitics CWS SiPEX values within 3% of Momentum baseline At least 2x speed up with pushbutton solution Up to 6x speed up using Calibre C+CC mode without accuracy loss 84 ports only practical with Mentor + CWS automated flow (*) Time includes best estimate of manual edition tasks Copyright CWS
15 Content IR Drop Vs. System-level Interferences CWS Expertise Accuracy and Performance Silicon Validation Conclusion Copyright CWS
16 N s serial rows Coff Measurement of Shunt Transistor in RF Switches N p parallel devices A shunt transistor is made of N s rows in series Each row has N p devices in parallel With a perfectly isolating silicon substrate, each individual device should act as a constant unit capacitance C unit independent of N p and N s C C * measured unit N N p s C C * unit measured N N s p Copyright CWS
17 C unit [ff] C unit [ff] C unit as a Function of N s and N p C unit with fixed N s =12 C unit with fixed N p =9 (W total =2.25mm) PEX Only Simulation Measurements (*) PEX Only Simulation Measurements (*) N p N s (*) Measurements courtesy of STMicroelectronics Copyright CWS
18 Device Coupling with Silicon Substrate C unit Measurement exhibits strong influence of N s and N p on C unit value C box SUB CWS SiPEX C box Silicon substrate parasitics need to be added in simulation environment CWS SiPEX flow used to fix accuracy with no performance degradation on extraction and simulation Copyright CWS
19 C unit [ff] C unit [ff] CWS Silicon Validation with C off Measurement* C unit with fixed N s =12 C unit with fixed N p =9 (W total =2.25mm) PEX Only Simulation Measurements (*) SiPEX Simulation PEX Only Simulation Measurements (*) SiPEX Simulation N p N s CWS provides easy simulation of physical impact on critical design metrics with high accuracy (*) Measurements courtesy of STMicroelectronics Copyright CWS
20 Content IR Drop Vs. System-level Interferences CWS Expertise Accuracy and Performance Silicon Validation Conclusion Copyright CWS
21 Conclusion CWS delivers innovative solutions to analyze systemlevel interferences Fast turn-around time Excellent accuracy Optimized and Fast Time-to- Market Physical Implementation Interactive exploration Available solution is qualified for Bulk CMOS, FD- and RF-SOI processes Copyright CWS
22 THANK YOU! Looking for more? Contact Visit
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