TSBCD025 High Voltage 0.25 mm BCDMOS

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1 TSBCD025 High Voltage 0.25 mm BCDMOS TSI Semiconductors' 0.25 mm process is a feature rich platform with best in class CMOS, LDMOS, and BiPolar devices. The BCD technology enables logic, Mixed-Signal, and High Voltage designs for a wide range of high-growth applications such as LED Lighting, Energy Management, Consumer White Goods, and Networking. Eight-inch wafers are manufactured using this process in an automotive qualified facility located in Roseville, CA. Key Features The process was developed such that significant die area reduction, and therefore lower die-cost, could be achieved. The process can offer >20% more die per wafer versus comparable foundry technologies. Feature rich BCD process 2.5V / 5.0V foundry compatible CMOS Scalable extended drain / lateral drain MOS from 15V to 80V Up to 6 levels of Al with a 3.3 mm ultra thick metal option Aggressive back-end design rules, similar to 0.18 mm, resulting in smaller die size Deep trench isolation (DTI) with excellent lateral isolation also for smaller die size DTI allows designers to float HV devices for use as both high and low side drivers across a substrate voltage range from -100 to +100V Applications Automotive Energy Management LED Lighting Networking Industrial Automation Consumer Micro-controllers, evehicles, hybrid vehicles, charging stations Photovoltaics, wind and solar meters, battery management, gate drivers Signage, street / traffic lighting, architectural, pixilated sources, drivers Power over Ethernet, power line communications, smart grid, base stations Smart building, home and industrial controls, smart sensors Digital power mgmt units, active-matrix organic LED displays, class D audio, IOT

2 Standard Cell and IO Libraries Library Feature Voltage Range Standard Cell Library I/O Cell Library 2.5V/5V I/O Cell Library 20V/40V/60V Analog I/O 9 Track, high density, multiple drive strength & highly optimized for synthesis, optional DTI for low noise and high/low side designs. Support for Circuit Under Pad (CUP) from 4LM to 6LM, inline and staggered bondpads, output frequency up to 100 Mhz, multiple (up to 8x) drive strength options, >2kV HBM Support for CUP from 4LM to 6LM, inline and staggered bondpads, output frequency up to 100Mhz, >2KV HBM 2.25V to 2.75V 2.5V/5V 20V/40V/60V Application ISSI OTP Memory 1 x 32 bits 1.6 to 2.0V Trim bits Signal path, power management, low power and low noise Pad limited & core limited designs Pad limited & core limited designs ISSI OTP Memory 8k x 8 bits 4.5 to 5.5V Parameters / Data TSI Single-Port SRAM sq. microns 2.5V +/- 10% Bit cell only TSI Dual-Port SRAM sq. microns 2.5V +/- 10% Bit cell only TSI's Design Advantages Deep Trench Isolation reduces die size, leakage current and allows for higher operating temperatures DTI 20-30% Area Reduction N-Isolation DTI Isolation Well DTI Isolation N-Isolation p-epi N type Buried Layer TSI Foundry TSI's 025BCD Back-End of Line (BEOL) is similar to 0.18 mm design rules and coupled with DTI, results in the potential for a 20%-30% die size area reduction.

3 BEOL Design Rules Comparison Design Rule Std 0.25mm BEOL Std 0.18mm BEOL 025BCD ~ [0.18mm] BEOL Contact Width/Space M1 Width/Space Via 1-5 CD/Space M2-5 Width/Space M6 (1mm) Width/Space VTM CD/Space M6 (3mm) Width/Space 0.3/ / / / /2 0.22/ / / / / /2 0.22/ / / / / / /1.9 Device Electrical Parameters TSBCD025 Core MOS Transistors Device 2.5V NMOS 2.5V NMOS - Isolated 2.5V PMOS 2.5V PMOS - Isolated 2.5V Native VT NMOS 2.5V Native VT NMOS - Isolated 5V NMOS 5V NMOS - Isolated 5V PMOS 5V PMOS - Isolated 5V Native VT NMOS 5V Native VT NMOS - Isolated W/L [mm] V T ID SAT [ma/mm] I I OFF l [pa/mm] I BV DSS I Max V DS Max V GS 10/ ± ±90 <250 6 ± / ± ±50 <150 6 ± / ± ±90 NA NA / ± ±80 < ± / ± ±40 < ± / ± ±190 NA NA TSBCD025 High Voltage LDMOS Transistors Device V T ID SAT [ma/mm] R ON * Area [ohm.mm2] I BV DSS I Max V DS 20V NDMOS > V NDMOS > V NDMOS > V NDMOS > V PDMOS > V PDMOS > V PDMOS > Max V GS

4 Metal Layer Options HV Device Benchmarked to Industry LDNMOS RDSOn vs. BVDSS RDSOn [mohms-mm 2 ] RV_0.25umBCD_LDNMOS Competitor 1 Competitor 2 Competitor 3 Competitor BVDSS Very competitive RDSon - TSBCD025 is useful for fast switching applications like power management.

5 Design Flow and Tools BCD25 PDK Cadence DFII (v5.1x). OA (6.1.6) Mentor Graphics Calibre (v2014.2_23.18) Cadence - Spectre, Spectre-Verilog Synopsis - HSPICE Layout/Schematic DRC/LVS/ERC/PEX SPICE & Verilog Simulation SPICE Simulation BCD 0.25 µm Design Collateral PDK, Standard Cell Lib, I/O Lib, Memory Digital HV/Analog/Mixed-Signal Synthesis (IC Compiler) Schematic Capture (Virtuoso) Simulation (Verilog) Simulation (Spectre, Hspice, Spectre-Verilog) Place & Route (IC Compiler, Encounter) Custom Layout (VXL) Analog P&R (Virtuoso GXL) Post Layout Simulations (Timing, Power, Integrity, Primetime, VPS) Simulations w/ Parasitics (Spectre/Hspice back annotation) Verification & Sign-off PDK Availability Logic and HV: V1.0 - Now Mixed Signal: V1.0 - March 2015 About TSI Semiconductors TSI Semiconductors offers world class analog and mixed signal foundry processes and services for RF, power management, high voltage, and high temperature automotive applications. TSI Semiconductors' experienced engineering teams also excel at installing customer-specific processes to meet our customers' requirements in analog and mixed signal applications. The complete array of services provided by TSI Semiconductors can take any set of specifications and create a totally transparent turnkey solution, from chipset development to fully qualified and packaged products. Headquarters TSI Semiconductors 7501 Foothills Blvd. Roseville, CA (916) Visit us online at tsisemi.com or drop us a line at foundry.sales@tsisemi.com