PRONTO Ultimum: Ultrathin Chips Embedded in Flexible Packages Thomas Gneiting, AdMOS GmbH

Transcription

1 PRONTO Ultimum: Ultrathin Chips Embedded in Flexible Packages Thomas Gneiting, AdMOS GmbH CST European User Conference 2013 April 23 25, 2013 Maritim Hotel Stuttgart/Liederhalle, Stuttgart, Germany Dr. Thomas Gneiting, Stefan Reck

2 Content 1. Introduction 2. General Simulation Flow 3. SPICE Transistor Models for Stress Effects 4. Simulations in CST Multi Physics Studio 5. Simulation Settings in CST2013

3 1. Introduction Silicon chip, thickness: um (Picture: Würth Elektronik) Flexible Substrate IMS Chips Stuttgart developed a method to manufacture ultra thin silicon chips with a thickness of only 10-20um. They can be placed on flexible substrates based on organic foils like Polyimide (PI) or Liquid Crystal Polymers (LCP) with a thickness of um. Both, chip and package are a highly flexible system.

4 1. Possible Application The picture shows a possible application of such a flexible ultrathin packaged system in medical technology. The idea is to have e.g. a sensor which is patched to the human skin to monitor certain indicator values. In this case, this sensor must be highly flexible as it will be placed directly at the human knee which can be bended. This research project was funded by the Federal Ministry of Education and Research (FKZ: 16SV5135). Partners are: Robert Bosch GmbH, Würth Elektronik, IMS Chips, AdMOS

5 1. Need of Different Simulation Analyses The following picture shows the principal cross section of a flexible substrate with an embedded ultrathin chip. The chip is connected to the metalization of the substrate through pillars or bumbs. The remaining space between chip and foil is underfilled. Ultra thin silicon chip Cover Interface between silicon chip and substrate. Flexible substrate The table on the following page shows the different simulation analyses which are necessary during the development phase of such a system.

6 1. Simulation Scenarios Part of the System Description Silicon chip: Change in the electrical behaviour of the CMOS transistors through mechanical stress Silicon chip and interface: mechanical stress due to bending Complete System: Self heating dueto electrical power dissipation Complete System: Mechanicalstress and deformation due to self heating Simulation Type SPICE circuit simulation 3D FEM Simulation Coupling SPICE circuit simulation- 3Dthermal simulation Coupling SPICE - 3D heat flow 3D mechanical stress

7 2. Simulation Flow 3D FEM Thermal Temperature T= f(x,y,z) 3D FEM Mechanical Power Dissipation P= f(x,y) Mechanical Tension σ= f(x,y,z) Power = f(block) SPICE circuit simulation Iteration not implemented SPICE simulation with changed electrical behavior due to stress related piezo effects in transistors

8 3. SPICE Transistor Models for Stress Effects Standard transistor models (BSIM3, PSP) do not cover the phenomenaof mechanical stress. To describe this effect, additional formulations were integrated by AdMOS into the Verilog- A code of the PSP MOS model. The new model was linked to standard simulators (HSPICE, Spectre) and was verified by experiments done in the labs of IMS-Chips, Stuttgart.The above diagram shows the saturation current of a NMOS transistor versus bending radius and orientation of the stress. (Picture: IMS Chips)

9 4. Simulations in CST Multi Physics Studio During this research project, the CST environment was used to perform mechanical stress simulations as well as combined thermal and mechanical simulations The goal of the combined electrical, thermal and mechanical simulations is to identify critical deformations and stress which are caused by electrical dissipation power on the silicon chip. The electrical power is converted into heat, which causes deformations and mechanical stress in the elements of the package. In a further step, which was not done yet, it could be imagined, that the flexible foil contains e.g. an antenna of a RFID system. Then a combined simulation scenario could be to simulate the changes in electrical behaviour of such an antenna in a deformed package. The following slides show the results as well as the procedures which have been applied in CST Multi Physics Studio

10 4. 3-D Model Flexibles System PI Substrate, size 50x50mm Top Layer metalization Test chip, 5x5mm

11 4. Details 3-D Modell Acrylat Si Chip Pillar Bumps Metal1 Chip Chip removed, Pillar bumps and lines

12 4. Deformation of Package and Silicon-Chip Deformed Package Original state (flat) The upper shown deformation is a result of a simulation, which represents a real experiment to determine the bending of such a packaged system. The force is introduced along a line in the middle of the package.

13 4. Analysis of Mechanical Tensions Large tensions can be seen in the bumps between the contacts on the chip and the substrate. Simulations will be linked to bending experiments, during where the electrical conductivity of a daisy-chain circuit through a lot of bumps is measured. An increase of resistance occurs shortly before the chain breaks

14 4. Result Thermal Simulation SPICE simulations of dedicated circuits resulted in a power dissipation of ca. 0.25W into the silicon of the chip. Temperature distribution in the top metal layer of the substrate and the package on a solid body.

15 4. Results combined thermal mechanical analysis Deformation of the chipsubstrate system through self heating (z values increased by a factor of 100). The maximum deformation is 0.2mm and is in the same order of magnitude than the thickness of the complete package. The more critical part in this analysis are the tensions through the temperature increase in the bumps between the chip and the package. The pictures show σ xx of the 2nd order Piola-Kirchoffstress tensor 2. This representation had to be selected due to the very strondeformations in this analysis.

16 5. Simulation Flow in CST2013 Setting up these kind of multi physics simulations is improved in CST We used a beta version to evaluate this problem. The screenshots in this page show the simulation control for a combined parametric analysis. The power dissipation Pchipis swept from 50mW to 250mW. For each value, first a thermal simulation is done which is then followed by a mechanical stress analysis. The results are recorded by post processing steps. It would be a further improvement, if the parameter sweep could be done in addition by a list of values instead of a linear sweep only. Due to the strong deformations, the highest accuracy settings had to be selected