RTL2GDS Low Power Convergence for Chip-Package-System Designs. Aveek Sarkar VP, Technology Evangelism, ANSYS Inc.

Transcription

1 RTL2GDS Low Power Convergence for Chip-Package-System Designs Aveek Sarkar VP, Technology Evangelism, ANSYS Inc.

2 Electronics Design Complexities Antenna Design and Placement Chip Low Power and Thermal FinFET Reliability Intel 22nm Tr.

3 Ongoing Innovation: HPC / Mobile / Automotive Intel Core M: 4X power savings 50% improved performance Electronics: 50+% of car s BOM (2020) A8: 50 percent more energy efficiency than A7 Projected worldwide sales of automotive MCUs (by volume)* *

4 Everything Emerging Innovations Low-cost Smartphones Q2_2014 ~ 300M units ~150+M were sub-$200 (IDC Worldwide Mobile Phone Tracker, August 14, 2014) IoT Devices Smart interconnected devices 50B by 2020? Sensors, processors, connectivity 51% growth over 5 years Consumer/Home Healthcare Retail Security Transportation Industrial. Sensors Gateway Cloud Apps

5 Common Design Challenges Mixed-signal Processing High-Fidelity Communication Cost Optimized Electronic Systems Fault-free Embedded Code Low Power Complexity Management Cost Reduction

6 Simulation for Virtual System Prototyping System Low Power Top Down Bottom Up Complexity Components Simulation driven prototyping Cost Multi-variable optimization Cross-function collaboration

7 Component Validation and Sign-off Using Simulation Converge on individual physics Optimize for multi-physics Create Share Electronic System Development Simulate Track Fix Analyze

8 Optimization Across All Ecosystem Partners Semiconductor Electronics Software Architecture IP Protected Data/Model Sharing Over or Under Design Unified System Virtual Prototyping Disjointed Simulation Flows System

9 Optimization Across All Ecosystem Partners Semiconductor Electronics Software Architecture IP Protected Data/Model Sharing Unified System Virtual Prototyping System

10 ANSYS Vision for Electronics Single Physics Single User Single Component Few Design Points Studied RTL Power IC Power Simulation Driven Product Development Multi-physics System Power System EMI System Timing Circuit AND System simulations Multi-User, Multi-Scale Parametric Optimization Design Exploration System Stress Antenna Radiation System Thermal

11 ANSYS Technologies for IC Design PowerArtist RedHawk Totem PathFinder RTL Design for Power Chip-Package Power, Noise and Reliability Analog, IP, Memory SoC and IP ESD IC + Pkg Board System IC Receiver

12 ANSYS Technologies for System HFSS SIwave Q3D Icepak 3D Full-Wave Sign-off BRD & PKG Analysis 3D Quasi-Static Modeling Electrical Thermal CPM DesignerSI Compact Application Specific Model Package Board System IC Receiver

13 Power (W) Design for Power Methodology Version 1 Version E E E E E E E+00 Version 2 (Typ) Version 1 (Typ) Version 2 (Idle) Version 1 (Idle) Perform design trade-offs TRANSMIT MODE RECEIVE MODE Residual receive activity in transmit mode Profile power vectors Peak Power = Average 391mW power = 239mW Check power vs. budget RTL Power Regression Flow Enabled Clock Inactive Data Debug power hotspots Reduce power automatically Monitor power vs. budget

14 Power Aware Design Power Budgeting Thermal Planning ~20 hours Design Specs. RTL Design Synthesis Gate Level Design ~20 mins Architectural Planning Design Implementation RTL Power Placement guidance Gate Power Thermalaware EM Early thermal analysis, planning Sign-off thermal simulations After 3 weeks on PowerArtist flow we reduced by 82% the power consumption from 44.3 µw to 7.8 µw while maintaining the initial area of 0.16 um2 for our UHF RFID digital baseband block.. SMDH, Brazil. Thermalaware EM Chip Thermal Profile System Thermal

15 Design for Performance and Cost RTL Development PowerArtist RedHawk IP Development Analysis Reduction Regression RPM Prototyping Design Development Sign-off Floorplan Soc Integration and Sign-off System Sign-off

16 Design for Performance and Cost RTL Development Resolve IP Design Issues IP Development Metal3 strap not extended Floorplan Soc Integration and Sign-off System Sign-off

17 Design for Performance and Cost RTL Development IP Development Floorplan Soc Integration and Sign-off System Sign-off Non-optimized uniform grid Design Dependent optimized grid Metal3 strap not extended CPU (100 mw) DSP (700 mw) DSP (700 mw) CPU (100 mw)

18 Design for Performance and Cost RTL Development IP Development Metal3 strap not extended Floorplan Soc Integration and and Sign-off System Sign-off

19 Design for Performance and Cost RTL Development IP Development Metal3 strap not extended Floorplan Soc Integration and and Sign-off System Sign-off

20 Power Delivery Optimization Prediction Reduction L R A B C D E Chip + Package On-chip Noise (from community.arm.com) Systemaware IC IC-aware System PCB, System PCB Supply Voltage

21 Reliability Sign-off Electro-migration (EM) Electro-static Discharge (ESD) Electro-magnetic Interference (EMI) Layout-Based Chip Emission Models Using RedHawk, Steinecke et al, Infineon. ESD/EOS Symposium, Samsung.

22 Case Study: Mixed-Signal Automotive IC Case study: NXP (Saturn SAF360X) Multi-standard software-defined radio co-processor capable of decoding all three major digital terrestrial radio standards 6 separate IC functions in one chip == 75% size reduction Coupling Noise from switching digital to sensitive analog through the silicon Noise coupling Spikes in FM Spectrum Impacts audio quality and performance Radio Processor SoC Cross-section

23 Case Study: Mixed-Signal Automotive IC Case study: NXP (Saturn SAF360X) Multi-standard software-defined radio co-processor capable of decoding all three major digital terrestrial radio standards 6 separate IC functions in one chip == 75% size reduction Coupling Noise from switching digital to sensitive analog through the silicon Radio Processor Improvement SoC Cross-section Noise Current Amplitude versus time

24 Enabling Technologies Foundry Certified Parasitic Extraction On-chip RLC, substrate RC, package RLCK Foundry certified and PDK enabled On-Chip Switching RTL/gate VCD or statistical VectorLess Mixed-mode analysis support Best-in-Class Capacity Full-chip capacity including substrate Distributed package model support Silicon Validated Sign-off Accuracy Time-domain pico-second resolution Silicon validated over multiple applications

25 Electronic System Design Coverage RTL Power Analysis Power Reduction Power Regression PowerArtist IP IP Reliability IP Power IP Modeling Totem SoC Connectivity Dynamic Voltage Static IR, EM ESD Signal EM Chip Models RedHawk PathFinder System Antenna Design Pkg, PCB Signal Integrity Power Integrity EMI, EMC Thermal HFSS Q3D SIwave Icepak

26 ありがとう Aveek Sarkar