ICS 252 Introduction to Computer Design

Transcription

1 ICS 252 Introduction to Computer Design Lecture 3 Fall 2006 Eli Bozorgzadeh Computer Science Department-UCI

2 System Model According to Abstraction level Architectural, logic and geometrical View Behavioral, structural, and physical Modeling means Language Diagram Mathematical model, etc 3

3 Hardware Modeling [ GDM] Specialized languages with hardware design support Multi-level abstractions Behavioral, structural, RTL. Support for simulation Is it software programming language design? Hardware versus software models Hardware Parallel Execution I/O ports, building blocks. Exact event timing is very important Software Sequential execution (usually) Structural information less important Exact event timing not important ICS 252-Intro to Computer Design 4

4 Hardware language vs. description view Structural view Composition of blocks Incidence structure Hierarchy and instantiation HDL examples: Verilog, VHDL Behavioral View Set of tasks with partial order Independent of implementation HDL examples: VHDL, Verilog 5

5 Abstract models Abstraction models Derived from language models by compilation Mathematical model Based on graph and Boolean algebra at architectural and logic level Behavior abstracted to Set of operations and dependencies (at architectural level), finite-state machine ( at logic level) Structure abstracted to Interconnection of logic blocks or gate (logic level) or resources (architectural level) Synthesis Abstract model concrete structure Not advocate the use of any specific hardware language, i.e. verilog or VHDL? 6

6 Examples [ GDM] Netlist Structural views Logic networks Mixed structural/behavioral views State diagrams Behavioral views of sequential logic models Dataflow and sequencing graphs Behavioral 7

7 Compilation and Synthesis Compilation Input language models abstract models Synthesis Abstract models concrete structures 8

8 Compilation and Synthesis Compilation spans prog. Language theory, arch and algorithms Synthesis spans finite automata, concurrency, and switching theory and algorithms In practice, they are inter-related. Indeed synthesis is referred to as silicon compilation. Three steps of compilation: Front-end Representation and optimization Back-end 9

9 HW and SW Compilation and Synthesis Program compilation for a software target: Front-end parsing into intermediate format Optimizations over the intermediate format Back-end code-generation for a given ISA HDL Compilation for a hardware target: Front-end parsing into intermediate format Optimization over the abstract model Back-end architectural/logic/physical synthesis [ Gupta] 10

10 Hardware compiler front-end Lexical Analysis Generation of a recognizable input to semantics analyzer Parser Generate parse tree for HDL (behavioral intermediate format (BIF)) Semantics Analysis Data flow, control flow, type checking, etc. 11

11 Behavioral Optimization Semantic-preserving transformations over the parse tree. Implemented as multi-pass traversals on BIF. On different types: Data flow graphs (DFG) Control flow graphs (CFG) Hardware synthesis oriented 12

12 Dataflow Graphs (DFG) [ GDM] Behavioral view of architectural models Useful to represent data paths Directed graph: Vertices: operations Edges: dependencies Example 13

13 Data flow-based transformations Tree height reduction Constant and variable propagation Common sub expression elimination Dead code elimination Operator strength reduction Code motion 14

14 Tree-height reduction Goal: exploit parallelism on hardware Related work in software compilation Local transformations in basic block Reduce the height of tree (best case:?) Based on Commutativity, Distributivity, and Associativity of arithmetic operators. 15

15 Constant and variable propagation Propagate constant and variables to reduce operations Constant propagation a = 0; b = a + 1;c = 2 * b; Variable propagation a = x; b = a + 1;c = 2 * a; [ Gupta] 16

16 Common sub-expression elimination Logic nodes Kernel extraction during logic optimizations Arithmetic nodes Search isomorphic patterns in the parse tree Example 17

17 Other transformations Dead-code elimination Eliminate operations that are not referred Identified by unreachable nodes Operator strength reduction Replace an operator by a lower cost operator Code motion Move assignments that are loop-invariant [ Gupta] 18

18 Sequencing graphs [ GDM] Behavioral view of architectural models Useful for represent data-path and control (CDFG) Extended dataflow graphs Serialization Hierarchy Control-flow commands Branches, loops Polar Source and sink 19

19 Examples CDFG with Iterations Branching Hierarchy 20

20 Control flow-based transformation Model expansion Conditional expansions Loop expansion Block-level transformation 21

21 Hardware synthesis oriented transformations Concurrency enhancing transformations Combinational conditional coalescing Etc. 22

22 Hardware Design Flow Architectural synthesis Logic synthesis Layout Synthesis Next lecture is on architectural synthesis Input format Objectives Optimizations and design tasks 23

23 Summary Hardware synthesis requires specialized language Hardware and software models of computation are different Abstract models Capture essential information Derivative from HDL models Useful to prove properties 24