Register Transfer Methodology II
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1 Register Transfer Methodology II Chapter 12 1
2 Outline 1. Design example: One shot pulse generator 2. Design Example: GCD 3. Design Example: UART 4. Design Example: SRAM Interface Controller 5. Square root approximation circuit Chapter 12 2
3 1. One shot pulse generator Sequential circuit divided into Regular sequential circuit: w/ regular next-state logic FSM: w/ random next-state logic FSMD: w/ both Division for code development; no formal definition; Some design can be coded in different types FSMD is most flexible One shot pulse generator as an example Chapter 12 3
4 Basic block diagram Chapter 12 4
5 Refined block diagram of FSMD Chapter 12 5
6 Regular sequential circuit. E.g., mod-10 counter Chapter 12 6
7 FSM. E.g., edge-detection circuit Chapter 12 7
8 FSMD. E.g., multiplier Chapter 12 8
9 One-shot pulse generator I/O: Input: go, stop; Output: pulse gois the trigger signal, usually asserted for only one clock cycle During normal operation, assertion of go activates pulse for 5 clock cycles If go is asserted again during this interval, it will be ignored If stop is asserted during this interval, pulse will be cut short and return to 0 Chapter 12 9
10 FSM implementation Chapter 12 10
11 Chapter 12 11
12 Chapter 12 12
13 Chapter 12 13
14 Regular sequential circuit implementation Based on a mod-5 counter Use a flag FF to indicate whether counter should be active Code difficult to comprehend Chapter 12 14
15 Chapter 12 15
16 FSMD Implementation Chapter 12 16
17 Chapter 12 17
18 Chapter 12 18
19 Comparison: FSMD is most flexible and easy to comprehend What happens to the following modifications The delay extend from 5 cycles to 100 ccyles The stop signal is only effective for the first 2 delay cycles and will be ignored otherwise Chapter 12 19
20 Programmable one-shot generator The desired width can be programmed. The circuit enters the programming mode when both go and stop are asserted The desired width shifted in via go in the next three clock cycles Chapter 12 20
21 Can be easily extended in ASMD chart How about FSM and regular sequential circuit? Chapter 12 21
22 2. GCD circuit GCD: Greatest Common Divisor E.g, gcd(1, 10)=1, gcd(12,9)=3 GCD without division: Chapter 12 22
23 Pseudo algorithm Chapter 12 23
24 Modified pseudo algorithm w/o while loop Chapter 12 24
25 ASMD chart Chapter 12 25
26 VHDL code Chapter 12 26
27 Chapter 12 27
28 Chapter 12 28
29 What is the problem of this code? Another observation Chapter 12 29
30 Chapter 12 30
31 What is the performance now? Can we do better with more hardware resources Chapter 12 31
32 Square root approximation circuit A example of data-oriented (computationintensive) application Equation: 0.125x and 0.5y corresponds to shift right 3 bits and 1 bit Chapter 12 32
33 Pseudo code: Chapter 12 33
34 Direct data-flow implementation Chapter 12 34
35 Chapter 12 35
36 Requires one adder and six subtractors Code contains only concurrent signal assignment statements The order is not important. Sequence of execution is embedded in the flow of data Chapter 12 36
37 Data flow graph Shows data dependency Node (circle): an operation Arches: input and output variables Note that there is limited degree of parallelism At most two operations can be perform simultaneously Chapter 12 37
38 RT methodology can be used to share the operator Tasks in converting a dataflow graph to an ASMD chart Scheduling: when a function (circle) can start execution Binding: which functional unit is assigned to perform the operation In square root algorithm, all operations can be performed by a modified addition unit No function unit is needed for shifting Chapter 12 38
39 Scheduling with two functional units Chapter 12 39
40 Scheduling with one functional unit Chapter 12 40
41 ASMD chart Chapter 12 41
42 Registers can be shared as well reduce the number of unique variables A variable can be reused if its value is no longer needed E.g., Chapter 12 42
43 Chapter 12 43
44 VHDL code Needs to manually code the data path two insure functional units sharing One unit for abs and min One unit for abs, min, - and + Can be implemented by using an adder/subtractor with special input and output routing circuits Chapter 12 44
45 Chapter 12 45
46 Chapter 12 46
47 Chapter 12 47
48 Chapter 12 48
49 High-level synthesis Convert a dataflow code into ASMD based code (RTL code). RTL code can be optimized for performance (min # clock cycles), area (min # functional units) etc. Perform scheduling, binding Minimize # registers and muxes Mainly for computation intensive applications (e.g., DSP) Chapter 12 49
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