A purely map procedure for two-level multiple-output logic minimization

Transcription

1 International Journal of Computer Mathematics Vol. 84, No. 1, January 2007, 1 10 A purely map procedure for two-level multiple-output logic minimization ALI M. RUSHDI* and OMAR M. BA-RUKAB Department of Electrical and Computer Engineering, King Abdulaziz University, PO Box 80204, Jeddah 21589, Saudi Arabia College of Telecommunications and Electronics, PO Box 2816, Jeddah, 21461, Saudi Arabia (Received 12 June 2005; revised version received 31 August 2006; accepted 9 November 2006) A pedagogical treatment of two-level multiple-output logic minimization is presented through a compact exposition of a novel manual fast procedure. This procedure is a purely map technique which generalizes the map procedure for single-output minimization. It requires neither the generation of the set of all paramount prime implicants, nor the construction of a cover matrix. Instead, it utilizes certain visual interactions between various groups of maps placed at distinct levels of a Hasse diagram, which is conveniently drawn in a Karnaugh map layout so that any parent map is easily visualized as adjacent to all its children maps. The present exposition is believed to enhance what is currently available in undergraduate texts, and is intended as a supplement to, rather than a replacement of, automated computational experience. An illustrative example demonstrates the proposed procedure for the dual cases of AND OR and OR AND minimizations. Keywords: Multiple-output minimization; Purely map procedure; Karnaugh map; Hasse diagram; Duality C.R. Category: B Introduction The design of a compact combinational switching network with multiple outputs is an important problem that frequently arises in logic design practice [1 6], and most educators consider it to be an essential ingredient of a first course on digital design within the computer engineering curriculum [7 15]. Many software packages for handling the aforementioned problem exist with some of them intended for educational purposes [14]. However, there is unanimous agreement that students will not achieve the desired competency in logic design solely by mastering the use of one or more of these packages. They need at least a glimpse of the theoretical basis of the design problem, and an acquaintance with some manual techniques for solving it. Recent popular textbooks on digital design offer different expositions of this problem which vary in depth, length, rigour, and the nature of the manual technique or procedure employed. *Corresponding author. arushdi@kau.edu.sa International Journal of Computer Mathematics ISSN print/issn online 2007 Taylor & Francis DOI: /

2 2 A. M. Rushdi and O. M. Ba-Rukab In many texts (e.g. [15]) students are not burdened with any particular details of collective minimization. Instead, they are instructed to apply separate or individual minimization and then try to identify obvious common product terms so as to share these between the pertinent output functions. Other texts [7, 10] introduce students to the classical method of collective minimization through a map derivation of all paramount prime implicants (PPIs), followed by the construction of a Quine McCluskey cover matrix and/or a presence or Petrick function for selecting a minimal subset of the set of all PPIs. This method requires further checking for irredundant connections if exact minimization is to be achieved. Some texts present a simplified version of the classical method in which the final solution is generated directly from the set of multiple-output prime implicants (MOPIs) without reducing the MOPI set to its subset of PPIs [8, 12, 13]. In this paper we present a class-tested pedagogical treatment of the problem of collective two-level multiple-output logic minimization through a brief exposition of a novel efficient procedure for tackling this problem. This procedure is a purely map heuristic which generalizes the Karnaugh map (K-map) procedure used in single-output minimization. In fact, the K-map procedure can be viewed as a short-cut technique for obtaining the minimal sum of a switching function without deriving the set of all its prime implicants or its complete sum (figure 1(a)). Likewise, the procedure proposed here is a short-cut technique for obtaining a minimal collective cover without the need to determine the set of all MOPIs or even its subset of PPIs (figure 1(b)). The proposed procedure retains a pure map nature as it avoids any resort to algebraic or tabular techniques in the form of a presence function or cover matrix, respectively. It is of a good pedagogical value because of the pictorial insight it provides, and because it leads to a natural understanding of pertinent terminology such as MOPIs and PPIs. All it requires of students is some repeated application of the familiar map heuristic and the implementation of a simple algorithm which handles visual interactions between various maps. These maps are grouped at distinct levels of a Hasse diagram, which is conveniently drawn in a K-map layout so that any parent map is easily visualized as adjacent to all its Figure 1. Comparison of (a) single-output minimization and (b) multiple-output minimization, stressing the short-cut nature of the proposed procedure.

3 Two-level multiple-output logic minimization 3 children maps. Another point of strength of the current procedure is that, unlike the classical method, it does not need a final filtering of irredundant connections as it avoids producing them from the outset. The procedure has been repeatedly tested and was invariably welcomed by students who were typically computer engineering majors with little introductory background in logic design. The procedure stated herein minimizes a set of functions given in disjunctive form and produces an AND OR implementation. To obtain an OR AND implementation, many texts (e.g. [15]) suggest the application of the same procedure to the complements of the original functions, with these complements being represented again in disjunctive forms. However, to stress the concept of duality, in this paper an OR AND implementation is obtained via a dual version of the current procedure applied to the original functions represented in conjunctive forms. The dual version of the procedure reads the same as the original version provided that any of the following words be replaced by the word in parentheses after it: implicant (implicate), product (sum), sum (product), term (alterm), disjunction (conjunction), conjunction (disjunction), 1 (0), 0 (1), AND (OR), OR (AND), asserted (negatively asserted), and so on. The rest of the paper is organized as follows. Section 2 outlines the classical method of collective minimization and sets the stage for understanding the technical terms used in latter sections. Section 3 presents the proposed procedure which employs the standard heuristic of map coverage and implements an easily understandable algorithm for handling interactions between various maps. A detailed example illustrating the proposed procedure and its dual is given in section 4. Section 5 compares the proposed procedure with similar procedures, and section 6 concludes the paper. 2. The classical exposition Classically, a pedagogical exposition of multiple output logic minimization for the set of n functions S ={f 1,f 2,...,f n } starts by forming the set S f ={f 1,f 2,...,f n,f 1 f 2,...,f n 1 f n,f 1 f 2 f 3,...,f 1 f 2 f 3 f n } of the products of the functions taken 1, 2, 3,...,nat a time. The number of elements of S f is n ( n = 2 k) n 1. k=1 The next step is to construct the set S n of multiple-output prime implicants (MOPIs) for S, which is the union of the sets S i,1 i 2 n 1, where S i contains all the prime implicants of element i of S f. Later, the set S n is replaced by an important subset thereof, which is the set S p of paramount prime implicants (PPIs). A PPI for the product T = f i1 f i2 f ik of functions is a prime implicant (PI) for T which is not a PI for any product of functions subsuming T. Minimization is achieved by selecting appropriate subsets of S p via tabular or algebraic techniques such as the Quine McClusky cover matrix or the Petrick function technique, respectively. Finally, the resulting networks are examined for possible deletion of unnecessary connections and subsequently selecting the most compact of the final networks [7].

4 4 A. M. Rushdi and O. M. Ba-Rukab 3. The proposed heuristic procedure We note the existence of a partial order or a hierarchy among the member products of the set S f. Elements of the set S f form a Boolean lattice, which is conveniently illustrated by an n-level directed graph, i.e. a Hasse diagram [16]. Figure 2 shows such a diagram for the case n = 3. A single arrow in the diagram indicates a parent child relationship, while a series of concatenated arrows indicates a more general and encompassing ancestor descendant relationship in which a product T i is a descendant (ancestor) of another product T j when T i subsumes (is subsumed by) T j. The arrangement of the product members of S f in a Hasse diagram is implicit in the classical representation (e.g. [7]). Nodes of the Hasse diagram are at levels i ranging from 1 to n. Leveli has ( n i) nodes, each of which is a map representing a product of i functions. The present heuristic constructs a hierarchy of maps, each of which represents a member of the set S f of function products. This hierarchy is explicitly illustrated by a Hasse diagram, which is constructed in a K-map layout as shown in figure 3 for the case n = 3. A map variable Y i {i = 1, 2, 3} in figure 3 is an indicator variable for the presence of the function f i in the pertinent product of functions. In fact, a cell of the K-map of figure 3 is itself a map representing a product of functions in which the function f i is present if Y i = 1 and is absent otherwise. The layout of figure 3 is useful because it is more compact than that of figure 2, and, more importantly, any parent map appears adjacent (on a toroidal surface) to all its children maps. In general, both the Karnaugh map and the Hasse diagram can serve as visual aids for representing a Boolean lattice, but the Karnaugh map is definitely more useful [17, 18]. The current procedure now covers asserted map entries using the well-known Figure 2. Hasse diagram for the product members of S f when n = 3. Figure 3. The Hasse diagram in figure 1 constructed in a K-map layout.

5 Two-level multiple-output logic minimization 5 map heuristic [7 15]. It then handles interactions between ancestor and descendant maps via the following algorithm. For l=ndownto 1 do begin (a) Cover all maps at level l individually using the standard map heuristic. (b) For every 1-cell that is covered in a certain map in step (a), the asserted entries of all corresponding cells in ancestor maps are crossed out or marked by a slash. A slashed 1 is equivalent to a don t care (d) in further processing. (c) For every map at level l, check any loop in a map T i for every slashed or crossed-out 1 it contains against the loop in a descendant map T j which caused the slash. If the latter loop does not cover any asserted cells other than those covered by the former one (e.g. if the latter loop is contained in the former one), it is transferred to map T j /T i (which represents a product of functions present in the product T j but not in the product T i ) and is checked for enlargement therein. Enlargement means the replacement of a particular loop by an admissible larger one that covers the original loop. (d) Repeat step (c) for transferred loops until no further loop transfer is possible. Note that such a transfer is only possible when a transferred loop contains slashed 1s while covering the loop that caused the slash(es). end. 4. An illustrative example The approach outlined in section 3 is used in the collective design of an AND OR multipleoutput network for three four-variable incompletely specified functions given in decimal notation as follows: f 1 (X 1,X 2,X 3,X 4 ) = SUM m(0, 1, 2, 9, 11, 12) + SUM d(40) (1) f 2 (X 1,X 2,X 3,X 4 ) = SUM m(0, 5, 11, 13, 14) + SUM d(2, 10, 15) (2) f 2 (X 1,X 2,X 3,X 4 ) = SUM m(1, 4, 9, 10, 11, 13, 14) + SUM d(5, 15). (3) Figure 4. The seven K-maps used in AND OR multiple-output minimization.

6 6 A. M. Rushdi and O. M. Ba-Rukab Figure 4 shows K-map representations of these functions and their products taken two or three at a time. There are (2 3 1) = 7 maps in figure 4 arranged according to the K-map layout of a Hasse diagram (figures 2 and 3), so that the ancestor descendant relationship between any two maps is quite evident. In forming the products in figure 4, the two identities 1 d = d and 0 d = 0 are invoked. Figure 4 uses solid loops to represent the paramount prime applicants included in the final solution, and uses dotted loops to represent the prime implicants that are included temporarily but later enlarged within the same map or transferred to another map. If a certain PI loop is the only loop covering a particular cell, then this loop is essential (at the stage of drawing it); this fact is acknowledged by inserting an asterisk in the uniquely covered cell. First, we cover the sole map at the lowest level (level 3), the map of f 1 f 2 f 3, using the essential PI loop P 1 = X 1 X 2 X 3, and then cross out the asserted entries of the cells covered by this loop in all ancestor maps, i.e. in all the remaining maps. Next, we go to level 2 and simultaneously cover the three maps of products f 1 f 2, f 1 f 3, and f 2 f 3. We add the PI loop P 2 = X 1 X 2 X 4 for map f 1 f 2 and cross out the asserted entries of Figure 5. The AND OR network obtained in figure 4.

7 Two-level multiple-output logic minimization 7 its two cells in the ancestor maps f 1 and f 2. Since there is no asserted entry within the P 2 loop in the f 1 f 2 map that is crossed out, there is no need to compare P 2 with earlier PIs in a descendant map. The next map to consider is that of product f 1 f 3 which contributes a PI loop P 3 = X 2 X 3 X 4 and a crossing out of the asserted cells within P 3 in the parent maps f 1 and f 3. The map f 2 f 3 requires two PI loops P 4 = X 1 X 3 and P 5 = X 2 X 3 X 4, and the entries of the asserted non-slashed cells within these loops in the parent maps f 2 and f 3 are crossed out. The cell X 1 X 2 X 3 X 4 within P 4 is crossed out since it is already covered by P 1 of map f 1 f 2 f 3. This means that P 1 is no longer needed for f 2 or f 3 and should be moved from map f 1 f 2 f 3 to map f 1, where it is checked for possible enlargement; however, no enlargement is found possible. The final stage of the process is now reached by covering the three individual maps at level 1. Of these maps, f 2 is already completely covered, f 1 is covered by a single PI loop P 6 = X 2 X 3 X 4, and f 3 is covered by another PI loop P 7 = X 1 X 2 X 3. The design is now complete with the resulting network (figure 5) achieving a minimum number of 10 gates (as a primary objective) and a corresponding minimum number of 31 connections (as a secondary objective), as can be verified using the minimizer Espresso [4, 11]. We now turn our attention to the dual procedure for the collective design of an OR AND multiple-output network for functions (1) (3). Figure 5 shows K-map representations of these functions and their sums taken two or three at a time. The 0 and d entries in these maps are shown explicitly, while the 1-entered cells are left blank. In forming the sums in figure 6, the two identities 0 d = d and 1 d = 1 are used. Figure 5 uses solid loops to represent the paramount prime implicates included in the final solution, and dotted loops to represent the prime implicates that are included temporarily but later enlarged within the same map or transferred to another map. First, cover the (f 1 f 2 f 3 ) map using the prime implicate loops P 1 = X 1 X 2 X 3 X 4, P 2 = X 1 X 2 X 3, and P 3 = X 1 X 3 X 4, and then cross out the negatively asserted entries of the cells covered by these loops in all other (ancestor) maps. Now, the three maps at level 2 are covered simultaneously. No loops are needed to cover the maps (f 1 f 2 )or(f 1 f 3 ). The prime implicate loop P 4 = X 1 X 3 X 4 is now added to cover the map (f 2 f 3 ), and the negatively asserted non-slashed entries within the loop P 4 in the f 2 and f 3 maps are crossed out. The fact that the cell (X 1 X 2 X 3 X 4 ) is already Figure 6. The seven K-maps used in the OR AND multiple-output minimization.

8 8 A. M. Rushdi and O. M. Ba-Rukab crossed out is a reminder that this has already been covered by loop P 1. This means that prime implicate P 1 is no longer needed for the OR gates of f 2 or f 3. The loop P 1 is transferred from the (f 1 f 2 f 3 ) map to the f 1 map, in which it is enlarged to loop P 1 = X 1 X 2 X 4. The design now reaches its final stage at level 1. Prime implicate loops P 5 = X 2 X 4 and P 6 = X 2 X 3 are added to cover the f 1 map. The P 6 loop has two slashed entries that have Figure 7. The OR AND network obtained in figure 6.

9 Two-level multiple-output logic minimization 9 been already covered by loop P 2 in the ancestor map (f 1 f 2 f 3 ). Therefore, P 2 is not needed for f 1 and is transferred to the (f 2 f 3 ) map, in which it is enlarged to the loop P 2 = X 1 X 3 and subsequently causes its negatively asserted entries within the f 3 map to be crossed out. Now, the loop P 2 has an additional slashed entry in the cell (X 1 X 2 X 3 X 4 ) which is due to coverage by the loop P 3 in the (f 1 f 2 f 3 ) map. Since the loop P 3 is contained within the loop P 2, it is not required for f 2 or f 3 and therefore is transferred to the f 1 map, in which no enlargement is possible. The remaining work is straightforward as it simply adds loops P 7 = X 2 X 3 X 4 and P 8 = X 1 X 2 X 4 to cover the f 2 map and loop P 9 = X 1 X 2 X 4 to cover the f 3 map. An examination of the slashed entries within these loops reveals that no loop transfer is possible and the design is complete. Figure 7 shows the resulting OR AND network which uses 12 gates and 35 input connections, and is verified to be minimal by Espresso. Therefore the minimal two-level network is the earlier AND OR network shown in figure Comparison with similar procedures The heuristic in Hong et al. [3] is similar to the present procedure, since both avoid the generation of all PPIs. However, while the procedure in Hong et al. [3] obtains its final solution from an initial solution by using certain subprocesses for iterative improvement, the current procedure does not apply iteration to a complete solution but allows a partial solution to evolve gradually towards a complete final solution. The current procedure generalizes the map technique of single-output minimization to handle the more difficult problem of multiple-output minimization as it originally stands, i.e. without attempting to simplify or reduce it. In contrast, other techniques proceed by initially converting the original problem into an equivalent problem such as minimization of a single incompletely specified auxiliary function with an additional input dimension equal to the number n of outputs [1, 3, 6], constrained minimization of a single completely specified auxiliary function with an additional input dimension of value (n 1) only [19], or obtaining the solution of a system of Boolean equations [18, 20, 21]. 6. Conclusion A novel and efficient manual procedure for two-level multiple-output logic minimization has been presented in this paper. This procedure offers a powerful visual aid that enables students to construct minimal or near-minimal solutions quickly by sharing terms (or alterms) among individual functions through a collective handling of the maps of these functions and their various products (or sums). All the maps considered are partially ordered by a Hasse diagram constructed in a K-map layout so that a parent child relation between two maps is manifested as an adjacency between their K-map cells. Two-way interactions between maps at different levels of the Hasse diagram are easily and pictorially implemented. A solution is achieved neatly and quickly without any need to generate the set of all MOPIs or all PPIs, to construct a cover matrix or a presence function, or to inspect resulting connections for possible deletions of redundant ones. In short, the technique proposed here is a pure map procedure, and is believed to be the natural generalization of the single-output K-map procedure to the multiple-output case. In conclusion, we note that the present procedure has been illustrated via a small example, although it is applicable to somewhat larger problems involving more input and output

10 10 A. M. Rushdi and O. M. Ba-Rukab variables [22]. We also reiterate that, from the pedagogical point of view, the present procedure should be viewed as a supplement rather than a replacement to automated computational experience in logic design. Such an experience can be obtained from a variety of software educational packages including different versions of Espresso [4, 11], LogicAid [15], and MAX Plus [14]. References [1] Muller, D.E., 1954, Application of Boolean algebra to switching circuit design and to error detection. IRE Transactions on Electronic Computers, EC-3, [2] Bartee, T.C., 1961, Computer design of multiple-output logical networks. IEEE Transactions on Electronic Computers, EC-10, [3] Hong, S.J., Cain, R.G. and Ostapko, D.L., 1974, MINI: a heuristic approach for logic minimization. IBM Journal of Research and Development, 18, [4] Brayton, R.K., Hachtel, G.D., McMullen, C. and Sangiovanni-Vincentelli, A., 1984, Minimization Algorithms for VLSI Synthesis (Boston, MA: Kluwer Academic). [5] Dagenais, M.R., Agrawal, V.K. and Rumin, N.C., 1986, McBoole: a new procedure for exact logic minimization. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, CAD-5, [6] Roth, J.P., 1999, Mathematical Design (New York: IEEE Press). [7] Muroga, S., 1979, Logic Design and Switching Theory (New York: John Wiley). [8] Hill, F.J. and Peterson, G.R., 1981, Introduction to Switching Theory and Logical Design, 3rd edn (New York: John Wiley). [9] McCluskey, E.J., 1986, Logic Design Principles (Englewood Cliffs, NJ: Prentice-Hall). [10] Douglas, L. and David, P., 1991, Design of Logic Systems, 2nd edn (London: Chapman & Hall). [11] Hill, F.J. and Peterson, G.R., 1993, Computer Aided Logical Design with Emphasis on VLSI, 4th edn (NewYork: John Wiley). [12] Unger, S.H., 1997, The Essence of Logic Circuits, 2nd edn (New York: IEEE Press). [13] Wakerly, J.F., 2001, Digital Design: Principles and Practice, 3rd edn (Upper Saddle River, NJ: Prentice-Hall). [14] Brown, S. andvranesic, Z., 2003, Fundamentals of Digital Logic with Verilog Design (New york: McGraw-Hill). [15] Roth, C.H., Jr, 2004, Fundamentals of Logic Design, 5th edn (Belmomt, CA: Brooks/Cole-Thomson Learning). [16] Kolman, B., Busby, R.C. and Ross, S.C., 2000, Discrete Mathematical Structures, 4th edn (Upper Saddle River, NJ: Prentice-Hall). [17] Rushdi,A.M., 1997, Karnaugh map. In: M. Hazewinkel (Ed.), Encyclopedia of Mathematics, SupplementVolume I (Dordrecht: Kluwer Academic), pp Available online at: (accessed 18 December 2006). [18] Rushdi, A.M., 2001, Using variable-entered Karnaugh maps to solve Boolean equations. International Journal of Computer Mathematics, 78, [19] Rushdi, A.M. and Ba-Rukab, O.M., 2003, Two-level multiple-output logic minimization using a single function. International Journal of Computer Mathematics, 80, [20] Brown, F.M., 2003, Boolean Reasoning: The Logic of Boolean Equations, 2nd edn (New York: Dover Publications). [21] Rushdi, A.M. and Ba-Rukab, O.M., 2003, Low-cost design of multiple-output switching circuits using map solutions of Boolean equations. Umm Al-Qura University Journal of Science Medicine Engineering, 15(2), [22] Rushdi, A.M. and Ba-Rukab, O. M., 2004, A map procedure for two-level multiple-output logic minimization. In: Proceedings of the 17th National Computer Conference, Al-Madinah Al-Munw warah, Saudi Arabia, pp