CS8803: Advanced Digital Design for Embedded Hardware

Size: px
Start display at page:

Transcription

1 CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim Website:

2 Design flow for HDL-based ASICs Design Specification 8 Post-synthesis Design Validation 2 Design Partition 9 Post-synthesis Timing Verification 3 Design Entry: Verilog Behavioral Modeling Test Generation and Fault Simulation 4 Simulation/Functional Verification Cell Placement, Scan Chain and Clock Tree Insertion, Cell Routing 5 Design Integration and Verification 2 Verify Physical and Electrical Design Rules 6 Pre-synthesis Sign-Off 3 Extract Parasitics 7 Synthesize and Map Gate-level Netlist 4 Design Sign-Off Production-ready Masks

3 Copyright 2, 23 MD Ciletti 6 COMBINATIONAL LOGIC Combinational logic forms Boolean functions of the input variables. The outputs at any time, t, are a function of only the inputs at time t. The variables are assumed to be binary. a b c d Combinational Logic y y 2 y 3 y = f (a, b, c, d) y 2 = f 2 (a, b, c, d) y 3 = f 3 (a, b, c, d) y 4 = f 4 (a, b, c, d) A binary variable may have a value of or. Later, the logic value system will be expanded to have more values to support a hardware description language. POSITIVE LOGIC: Low voltage corresponds to logic and a high voltage corresponds to a logic.

4 Copyright 2, 23 MD Ciletti 7 LOGIC GATES And Gate y = a. b Or Gate y = a + b Xor Gate y = a ^ b a b y a b y a b y Nand Gate y = a. b Nor Gate y = a + b Xnor Gate y = a ^ b a b y a b y a b y Buffer y = a Inverter y = a Three-State Buffer y = a if ENB =, else y = z a y a y a y ENB

5 CHAPTER IV-3 GATE DESIGN GATE NETWORKS VALID/INVALID NETWORKS GATE NETWORKS -INTRODUCTION G G 2 G G 3 G 3 G 6 G 2 Valid or Invalid? Valid or Invalid? G G 3 G G 3 G 2 Valid or Invalid? G 2 Valid or Invalid? R.M. Dansereau; v..

6 CHAPTER IV-7 GATE DESIGN LOGIC NETWORKS FROM BOOLEAN FUNCTIONS LOGIC GATES -NON-INVERTING OPER. -INVERTING OPERATORS -INVERTERS Implement the following Boolean function using logic gates F = (( A + BC)D) + C+ DE Possible solution: A B C D E F 3 6 AND OR NOT = 42 transistors for CMOS technology. R.M. Dansereau; v..

7 CHAPTER IV-8 GATE DESIGN LOGIC NETWORKS USING SPECIFIC GATES LOGIC GATES LOGIC NETWORKS -FROM BOOL. FUNCTIONS Because of various implementation reasons, it may be desired to use only specific sorts of logic gates in an implementation. For instance, many CMOS implementations use only NAND gates. Some implementations use on NOR gates. This can be done in a number of manners. One is to rework the Boolean functions so that only the specific gates desired are used. May reduce the physical number of transistors required if the appropriate types of gates are used. R.M. Dansereau; v..

8 CHAPTER IV-9 GATE DESIGN LOGIC NETWORKS EXAMPLE USING NAND GATES LOGIC GATES LOGIC NETWORKS -FROM BOOL. FUNCTIONS -USING SPECIFIC GATES Implement the following Boolean function using NAND gates F = (( A + BC)D) + C+ DE This Boolean function can be expressed as F = ABCDCDE = ((( A ( BC ) ) D)( C )( DE) ) A B How to implement 4-input NAND? C D E 6 4 NAND NAND-4 = NAND NAND NOT = 26 F transistors transistors R.M. Dansereau; v..

9 CHAPTER IV- GATE DESIGN MIXED LOGIC INTRODUCTION LOGIC NETWORKS -FROM BOOL. FUNCTIONS -USING SPECIFIC GATES -EXAMPLE USING NAND Mixed logic is one approach that makes it easier to redesign a logic network to use desired types of gates. Mixed logic is also self-documenting This means that you can see what the original designer started with and see how the logic network was changed for the implementation. The idea behind mixed logic is to diagram out the logic network from the Boolean equations given, and then make small changes to the logic network to achieve desired results for implementation. R.M. Dansereau; v..

10 CHAPTER IV- GATE DESIGN MIXED LOGIC DEMORGAN S SQUARE LOGIC NETWORKS MIXED LOGIC -INTRODUCTION DeMorgan s Square AND OR A B F A B F NAND NOR A B F A B F R.M. Dansereau; v..

11 CHAPTER IV-2 GATE DESIGN MIXED LOGIC MIXED LOGIC PROCEDURE LOGIC NETWORKS MIXED LOGIC -INTRODUCTION -DEMORGAN S SQUARE The procedure for performing mixed logic conversions is as follows: Draw the logic network for the given Boolean equation. Use only AND and OR gates. Replace all complements with a bar (no bubbles or inverters yet!) Once the initial Boolean equation is drawn with AND gates, OR gates and bars, the self-documenting redesign begins: Add complement bubbles and NOT gates within the network to appropriately convert logic gates to desired gate sets. The rules in adding complement bubbles and NOT gates All bubbles must cancel each other out Exactly one and only one bubble needed on each bar R.M. Dansereau; v..

12 CHAPTER IV-3 GATE DESIGN MIXED LOGIC EXAMPLE # () MIXED LOGIC -INTRODUCTION -DEMORGAN S SQUARE -MIXED LOGIC PROC. Implement the following Boolean function using NAND gates and then also using NOR gates. Solution: Start by drawing the logic network for the Boolean function with A B C D the complements as bars. F = AB + CD This completes the information needed to get back original equation. F R.M. Dansereau; v..

13 CHAPTER IV-4 GATE DESIGN MIXED LOGIC EXAMPLE # (2) MIXED LOGIC -DEMORGAN S SQUARE -PROCEDURE -EXAMPLE # continued... using NAND gates A B F C D This logic network now only uses NAND gates and inverters. This results in the following Boolean function, as obtained previously F( A, B, C, D, E) = ABCD R.M. Dansereau; v..

14 CHAPTER IV-5 GATE DESIGN MIXED LOGIC EXAMPLE # (3) MIXED LOGIC -DEMORGAN S SQUARE -PROCEDURE -EXAMPLE # continued... using NOR gates A B F C D This logic network now only uses NOR gates and inverters. This results in the following Boolean function, as obtained previously F( A, B, C, D, E) = A + B + C + D R.M. Dansereau; v..

15 CHAPTER IV-6 GATE DESIGN MIXED LOGIC EXAMPLE #2 () MIXED LOGIC -DEMORGAN S SQUARE -PROCEDURE -EXAMPLE # Implement the following Boolean function using NAND gates F = (( A + BC)D) + C+ DE Solution: Start by drawing the logic network for the Boolean function with the complements as bars. A B C D E F R.M. Dansereau; v..

16 CHAPTER IV-7 GATE DESIGN MIXED LOGIC EXAMPLE #2 (2) MIXED LOGIC -PROCEDURE -EXAMPLE # -EXAMPLE #2 continued... A B C D E F This logic network now only uses NAND gates and inverters. This results in the following Boolean function, as obtained previously F( A, B, C, D, E) = ABCDCDE = ABCDCDE R.M. Dansereau; v..

17 Copyright 2, 23 MD Ciletti 9 BOOLEAN ALGEBRA (p 6) A binary Boolean algebra consists of a set B = {, } and the operators + and., having commutative and distributive properties such that for two Boolean variables A and B having values in B, a + b = b + a, and a. b = b. a. The operators + and. have identity elements and, respectively, such that for any Boolean variable a, a + = a, and a. = a. Each Boolean variable a has a complement, denoted by a', such that a + a' =, and a. a' =. Terminology: + is called the sum operator, the "OR" operator, or the disjunction operator.. is called the product operator, the "AND" operator, or the conjunction operator. The multi-dimensional space spanned by a set of n binary-valued Boolean variables is denoted by B n. A point in B n is called a vertex of and is represented by an n-dimensional vector of binary valued elements, e.g. (). A binary variable can be associated with the dimensions of a binary Boolean space, and a point is identified with the values of the variables.

18 Copyright 2, 23 MD Ciletti BOOLEAN FUNCTIONS A completely specified m-dimensional Boolean function is a mapping from B n into B m, denoted by f: B n B m. An incompletely specified function is defined over a subset of B n, and is considered to have a value of "don't-care" at points outside of the subset of definition: f: B n {,, *}, where * denotes don't-care. "On" Set: {x: x B n and f(x) = } "Off" Set: {x: x B n and f(x) = } "dc" Set: {x: x B n and f(x) = * } The don't-care set accommodates input patterns that never care, or outputs that will not be observed.

19 CHAPTER III-7 BOOLEAN ALGEBRA BOOLEAN ALGEBRA BASIC IDENTITIES BOOLEAN OPERATIONS BOOLEAN ALGEBRA -PRECEDENCE OF OPER. -FUNCTION EVALUATION X + = X X + = X + X = X X + X = ( X ) = X X + Y = Y + X X + ( Y + Z) = ( X + Y) + Z XY ( + Z) XY + XZ X X + XY = X + X Y = X + Y ( X + Y) = X Y X = X X = X X X = XY = YX XYZ ( ) = ( XY)Z = X + YZ = ( X + Y) ( X + Z) X = X XX ( + Y) = X XX ( + Y) = XY ( XY) = X + Y XY + X Z + YZ ( X + Y) ( X + Z) ( Y + Z) = XY + X Z = ( X + Y) ( X + Z) Identity Idempotent Law Complement Involution Law Commutativity Associativity Distributivity Absorption Law Simplification DeMorgan s Law Consensus Theorem R.M. Dansereau; v..

20 CHAPTER III-8 BOOLEAN ALGEBRA BOOLEAN ALGEBRA DUALITY PRINCIPLE BOOLEAN ALGEBRA -PRECEDENCE OF OPER. -FUNCTION EVALUATION -BASIC IDENTITIES Duality principle: States that a Boolean equation remains valid if we take the dual of the expressions on both sides of the equals sign. The dual can be found by interchanging the AND and OR operators along with also interchanging the s and s. This is evident with the duals in the basic identities. For instance: DeMorgan s Law can be expressed in two forms ( X + Y) = X Y as well as ( XY) = X + Y R.M. Dansereau; v..

21 Copyright 2, 23 MD Ciletti 7 REPRESENTATION OF COMBINATIONAL LOGIC Common representations of combinational logic: Truth Table Boolean Equations Binary Decision Diagrams Circuit Schematic EXAMPLE: HALF-ADDER TRUTH TABLE Inputs Outputs a b c_out sum a b Add_half sum c_out a b sum c_out

22 Copyright 2, 23 MD Ciletti 8 REPRESENTATION OF COMBINATIONAL LOGIC (Cont.) EXAMPLE: HALF-ADDER BOOLEAN EQUATIONS sum = a'b + ab' = a b c_out = a. b a b Add_half sum c_out a b sum c_out

23 CHAPTER III-4 BOOLEAN ALGEBRA STANDARD FORMS SUM OF MINTERMS BOOLEAN ALGEBRA STANDARD FORMS -SOP AND POS -MINTERMS Sum-of-minterms standard form expresses the Boolean or switching expression in the form of a sum of products using minterms. For instance, the following Boolean expression using minterms FABC (,, ) = ABC + ABC + ABC + ABC could instead be expressed as FABC (,, ) = m + m + m 4 + m 5 or more compactly FABC (,, ) = m(,, 4, 5) = one-set(,, 4, 5) R.M. Dansereau; v..

24 CHAPTER III-6 BOOLEAN ALGEBRA STANDARD FORMS PRODUCT OF MAXTERMS STANDARD FORMS -MINTERMS -SUM OF MINTERMS -MAXTERMS Product-of-maxterms standard form expresses the Boolean or switching expression in the form of product of sums using maxterms. For instance, the following Boolean expression using maxterms FABC (,, ) = ( A+ B+ C) ( A+ B+ C) ( A+ B + C) could instead be expressed as FABC (,, ) = M M 4 M 7 or more compactly as FABC (,, ) = M(, 4, 7) = zero-set(, 4, 7) R.M. Dansereau; v..

25 CHAPTER III-7 BOOLEAN ALGEBRA STANDARD FORMS MINTERM AND MAXTERM EXP. STANDARD FORMS -SUM OF MINTERMS -MAXTERMS -PRODUCT OF MAXTERMS Given an arbitrary Boolean function, such as FABC (,, ) = AB + B( A + C) how do we form the canonical form for: sum-of-minterms Expand the Boolean function into a sum of products. Then take each term with a missing variable X and AND it with X + X. product-of-maxterms Expand the Boolean function into a product of sums. Then take each factor with a missing variable X and OR it with XX. R.M. Dansereau; v..

26 CHAPTER III-8 BOOLEAN ALGEBRA STANDARD FORMS FORMING SUM OF MINTERMS STANDARD FORMS -MAXTERMS -PRODUCT OF MAXTERMS -MINTERM & MAXTERM Example FABC (,, ) = AB + B( A + C) = AB + AB + BC = AB( C + C) + AB( C + C) +( A + A)BC = ABC + ABC + ABC + ABC + ABC = m(,, 4, 6, 7) A B C F Minterms listed as s in Truth Table R.M. Dansereau; v..

27 CHAPTER III-9 BOOLEAN ALGEBRA STANDARD FORMS FORMING PROD OF MAXTERMS STANDARD FORMS -PRODUCT OF MAXTERMS -MINTERM & MAXTERM -FORM SUM OF MINTERMS Example F( A, B, C) = AB + B( A + C) = AB + AB + BC = = = = ( A + B) ( A + B + C) ( A + B + C) ( A + B + CC) ( A+ B+ C) ( A+ B+ C) ( A + B + C) ( A + B + C) ( A + B + C) M( 2, 3, 5) A B C F (using distributivity) Maxterms listed as s in Truth Table R.M. Dansereau; v..

28 CHAPTER III-2 BOOLEAN ALGEBRA STANDARD FORMS CONVERTING MIN AND MAX STANDARD FORMS -MINTERM & MAXTERM -SUM OF MINTERMS -PRODUCT OF MAXTERMS Converting between sum-of-minterms and product-of-maxterms The two are complementary, as seen by the truth tables. To convert interchange the and, then use missing terms. Example: The example from the previous slides FABC (,, ) = m(,, 4, 6, 7) is re-expressed as F( A, B, C) = M( 2, 3, 5) where the numbers 2, 3, and 5 were missing from the minterm representation. R.M. Dansereau; v..

29 Copyright 2, 23 MD Ciletti 26 SIMPLIFICATION OF BOOLEAN EXPRESSIONS (Cont.) A Boolean expression in SOP form is said to be minimal if it contains a minimal number of product terms and literals (i.e. a given term cannot be replaced by another that has fewer literals). A minimum SOP form corresponds to a two-level logic circuit having the fewest gates and the fewest number of gate inputs. A Boolean expression in POS form is said to be minimal of it contains a minimal number of factors and literals (i.e. a given factor cannot be replace by another having fewer literals). Three approaches: () Karnaugh maps and extended karnaugh maps (Feasible for up to 6 variables) (2) Quine-McCluskey minimization (computer-based) (3) Boolean minimization (manual) uses the theorems describing relationships between Boolean variables to find simpler equivalent expressions (It is not straightforward, is not easy, and requires experience. Now embedded in synthesis tools such as mis II.)

30 CHAPTER III-2 BOOLEAN ALGEBRA SIMPLIFICATION KARNAUGH MAPS STANDARD FORMS -SUM OF MINTERMS -PRODUCT OF MAXTERMS -CONVERTING MIN & MAX Often it is desired to simplify a Boolean function. A quick graphical approach is to use Karnaugh maps. 2-variable Karnaugh map 3-variable Karnaugh map 4-variable Karnaugh map CD AB A B BC A F = AB F = AB + C F = AB + CD R.M. Dansereau; v..

31 CHAPTER III-22 BOOLEAN ALGEBRA SIMPLIFICATION KARNAUGH MAP ORDERING STANDARD FORMS SIMPLIFICATION -KARNAUGH MAPS Notice that the ordering of cells in the map are such that moving from one cell to an adjacent cell only changes one variable. 2-variable Karnaugh map 3-variable Karnaugh map 4-variable Karnaugh map CD D D D AB BC A B C C C 3 2 A A A 3 2 A A 2 3 A A 8 9 B B B B C C B B B This ordering allows for grouping of minterms/maxterms for simplification. R.M. Dansereau; v..

32 CHAPTER III-23 BOOLEAN ALGEBRA SIMPLIFICATION IMPLICANTS STANDARD FORMS SIMPLIFICATION -KARNAUGH MAPS -KARNAUGH MAP ORDER Implicant Bubble covering only s (size of bubble must be a power of 2). Prime implicant Bubble that is expanded as big as possible (but increases in size by powers of 2). Essential prime implicant Bubble that contains a covered only by itself and no other prime implicant bubble. Non-essential prime implicant A that can be bubbled by more then one prime implicant bubble. CD AB R.M. Dansereau; v..

33 CHAPTER III-24 BOOLEAN ALGEBRA SIMPLIFICATION PROCEDURE FOR SOP SIMPLIFICATION -KARNAUGH MAPS -KARNAUGH MAP ORDER -IMPLICANTS Procedure for finding the SOP from a Karnaugh map Step : Form the 2-, 3-, or 4-variable Karnaugh map as appropriate for the Boolean function. Step 2: Identify all essential prime implicants for s in the Karnaugh map Step 3: Identify non-essential prime implicants for s in the Karnaugh map. Step 4: For each essential and one selected non-essential prime implicant from each set, determine the corresponding product term. Step 5: Form a sum-of-products with all product terms from previous step. R.M. Dansereau; v..

34 CHAPTER III-26 BOOLEAN ALGEBRA SIMPLIFICATION EXAMPLE FOR SOP (2) SIMPLIFICATION -IMPLICANTS -PROCEDURE FOR SOP -EXAMPLE FOR SOP Simplify the following Boolean function FABC (,, ) = m(,, 4, 6, 7) = ABC + ABC + ABC + ABC + ABC Solution: BC A zero-set( 235,, ) one-set(,, 4, 6, 7) The essential prime implicants are AB and AB. The non-essential prime implicants are BC or AC. The sum-of-products solution is F = AB+ AB+ BC or F = AB+ AB+ AC. R.M. Dansereau; v..

35 CHAPTER III-27 BOOLEAN ALGEBRA SIMPLIFICATION PROCEDURE FOR POS SIMPLIFICATION -IMPLICANTS -PROCEDURE FOR SOP -EXAMPLE FOR SOP Procedure for finding the SOP from a Karnaugh map Step : Form the 2-, 3-, or 4-variable Karnaugh map as appropriate for the Boolean function. Step 2: Identify all essential prime implicants for s in the Karnaugh map Step 3: Identify non-essential prime implicants for s in the Karnaugh map. Step 4: For each essential and one selected non-essential prime implicant from each set, determine the corresponding sum term. Step 5: Form a product-of-sums with all sum terms from previous step. R.M. Dansereau; v..

36 CHAPTER III-29 BOOLEAN ALGEBRA SIMPLIFICATION EXAMPLE FOR POS (2) SIMPLIFICATION -EXAMPLE FOR SOP -PROCEDURE FOR POS -EXAMPLE FOR POS Simplify the following Boolean function F( A, B, C) = M(,, 5, 7, 8, 9, 5) Solution: The essential prime implicants are B + C and B+ C+ D. The non-essential prime implicants can be A + B + D or A+ C+ D. The product-of-sums solution can be either F = ( B+ C) ( B+ C+ D) ( A + B + D) or F = ( B+ C) ( B+ C+ D) ( A + C + D) zero-set(,, 5, 7, 8, 9, 5) one-set( 2, 3, 4, 6,,, 2, 3, 4) CD AB R.M. Dansereau; v..

37 CHAPTER III-3 BOOLEAN ALGEBRA SIMPLIFICATION DON T-CARE CONDITION SIMPLIFICATION -EXAMPLE FOR SOP -PROCEDURE FOR POS -EXAMPLE FOR POS Switching expressions are sometimes given as incomplete, or with don tcare conditions. Having don t-care conditions can simplify Boolean expressions and hence simplify the circuit implementation. Along with the zero-set () and one-set (), we will also have dc (). Don t-cares conditions in Karnaugh maps Don t-cares will be expressed as an X or - in Karnaugh maps. Don t-cares can be bubbled along with the s or s depending on what is more convenient and help simplify the resulting expressions. R.M. Dansereau; v..

38 CHAPTER III-3 BOOLEAN ALGEBRA SIMPLIFICATION DON T-CARE EXAMPLE () SIMPLIFICATION -PROCEDURE FOR POS -EXAMPLE FOR POS -DON T-CARE CONDITION Find the SOP simplification for the following Karnaugh map CD AB dc(, 3, 4) X X Taken to be X Taken to be Solution: The essential prime implicants are BD and BC. There are no non-essential prime implicants. The sum-of-products solution is F = BC+ BD. zero-set(,, 5, 7, 8, 9, 5) one-set( 2, 3, 4, 6,, 2) R.M. Dansereau; v..

39 CHAPTER III-32 BOOLEAN ALGEBRA SIMPLIFICATION DON T-CARE EXAMPLE (2) SIMPLIFICATION -EXAMPLE FOR POS -DON T-CARE CONDITION -DON T-CARE EXAMPLE Find the POS simplification for the following Karnaugh map CD AB dc(, 3, 4) Taken X X X Taken to be to be Solution: The essential prime implicants are B + C and B + D. There are no non-essential prime implicants. The product-of-sums solution is F = ( B+ C) ( B + D). zero-set(,, 5, 7, 8, 9, 5) one-set( 2, 3, 4, 6,, 2) R.M. Dansereau; v..

40 GLITCHES AND STATIC HAZARDS (p 42) Copyright 2, 23 MD Ciletti 5 The output of a combinational circuit may make a transition even though the patterns applied at its inputs do not imply a change. These unwanted switiching transients are called "glitches." Glitches are a consequence of the circuit structure and the application of patterns that cause the glitch to occur. A circuit in which a glitch may occur under the application of appropriate inputs signals is said to have a hazard. A static -hazard occurs if an output has an initial value of, and an input pattern that does not imply an output transition causes the output to change to and then return to. -Hazard A static -hazard occurs if an output has an initial value of, and an input pattern that does not imply an output transition causes the output to change to and then return to. -Hazard

41 GLITCHES AND STATIC HAZARDS Copyright 2, 23 MD Ciletti 52 Static hazards are caused by differential propagation delays on reconvergent fanout paths. A "minimal"realization of a circuit might not be hazard-free. Static hazards can be eliminated by introducing redundant cubes in the cover of the output expression (the added cubes are called a hazard cover).

42 Copyright 2, 23 MD Ciletti 53 STATIC HAZARDS: Example A C F F Reconvergent fanout paths B F Consider F = AC + BC' Initial inputs: A =, B =, C = and F = New inputs: A =, B =, C = and F = In a physical realization of the circuit (i.e. non-zero propagation delays), the path to F will be longer than the path to F, causing a change in C to reach F later than it reaches F. Consequently, when C changes from to, the output undergoes a momentary transition to and returns to. The presence of a static hazard is apparent in the Karnaugh map of the output.

43 STATIC HAZARDS: Example (Cont.) Copyright 2, 23 MD Ciletti 54 Hazards might not be significant in a synchronous sequential circuit if the clock period can be extended. y Static -Hazard occurs when F and F are both momentarily. A hazard is problematic if the signal serves as the input to an asynchronous subsystem. (e.g a counter or a reset circuit). In this example, the hazard occurs because the cube AC is initially asserted, while BC' is not. The switched input causes AC to de-assert before BC' can assert. C AB F = AC + BC' C AB Redundant cube Hazard Removal: A hazard can be removed by covering the adjacent prime implicants by a redundant cube (AB, a 'hazard cover") to eliminate the dependency on C (the boundary between the cubes is now covered). AC de-asserts before BC' asserts

44 Copyright 2, 23 MD Ciletti 55 STATIC HAZARDS: Example (Cont.) Hazard covers require extra hardware. Example: For the hazard-free cover: F = AC + BC' + AB A C F B

45 Copyright 2, 23 MD Ciletti 56 ELIMINATION OF STATIC HAZARDS (SOP Form) If the output cubes of the initial and final inputs are covered by the same prime implicant, a glitch cannot occur. Otherwise, if the output cubes of the initial and final inputs are not covered by the same prime implicant a glitch can occur, depending on the accumulated delays along the signal propagation paths from the inputs to the output. For a circuit whose static -hazard is caused by a transition in a single bit of a single signal: Form a SOP cover in which every pair of adjacent s is covered by a cube. This gurantees that every single-bit input change is covered by such a prime implicant. The set of prime implicants is a hazard-free cover for a two-level (And-Or) realization of the circuit, but a better alternative might be found.

46 Copyright 2, 23 MD Ciletti 57 ELIMINATION OF STATIC HAZARDS (Cont.) To eliminate a static -hazard: Method #: Cover the adjacent s in the corresponding POS expression. Method #2: First eliminate the static -hazards. Then form complement function and consider whether the implicants of the s of the expression that is free of static -hazards also cover all adjacent s of the original function. If they do not, then a static -hazard exists.

47 Copyright 2, 23 MD Ciletti 58 EXAMPLE: ELIMINATION OF STATIC HAZARDS Static -hazard: f = Σ m(,, 4, 5, 6, 7, 4, 5) = a'c' + bc Static -hazard (First method): From s of the K-map and DeMorgan's Law: f' = ac' + b'c and f = (a' + c) (b + c') a'c' cd ab m m m3 m2 m4 m5 m7 m6 m2 m3 m5 m4 m8 m9 m m Cover the cube boundaries by adding a'bd or a'b to eliminate the static - hazard bc cd ab m m m3 m2 m4 m5 m7 m6 m2 m3 m5 m4 m8 m9 m m Cover by adding (a' + b) to eliminate static- hazard Note: ab'd covers too, but is not mimimal f = a'c' + bc + a'b With a =, b =, and D =, a glitch can occur as c changes from to or visa-versa. Adding the redundant prime implicant term eliminates the static -hazard. Note: m 4 and m 6 interface f = (a' + c) (b + c') (a' + b) Add a'b to f', and including the redundant prime implicant product factor (a' + b) in f to eliminate the static -hazard.

48 DYNAMIC HAZARDS (Multiple glitches) Copyright 2, 23 MD Ciletti 6 A circuit has a dynamic hazard if an input transition is supposed to cause a single transition in an output, but causes two or more transitions before reached its expected value. Dynamic Hazard Dynamic hazards are a consequence of multiple static hazards caused by multiply reconvergent paths in a multilevel circuit. Dynamic hazards are not easy to eliminate. Elimination of all static hazards eliminates dynamic hazards. Approach: Transform a multilevel circuit into a two-level circuit and eliminate all of the static hazards.

49 CHAPTER VI-4 COMBINATIONAL LOGIC MULTIPLEXERS BASIC MULTIPLEXER (MUX) ENCODERS -DESIGN W/ ENCODERS -PRIORITY ENCODERS -DESIGN W/ P-ENCODERS Selects one of many inputs to be directed to an output. Module Enable Inputs E X Y A 3 A 2 A A A X X X X X X A X X X f 2 X X X A 2 A 3 3 4x Multiplexer S S X Y X X X X X X X X X X X X Output F A = A = A 2 = A 3 = A = A = A 2 = A 3 = R.M. Dansereau; v..

50 CHAPTER VI-5 COMBINATIONAL LOGIC MULTIPLEXERS USING PASS GATES ENCODERS MULTIPLEXERS -BASIC MULTIPLEXER The 4x mux can be implemented with pass gates as follows. Y X A A Out (f) A 2 A 3 Only one of A n gets passed to output. Depends on the value of X and Y. R.M. Dansereau; v..

51 CHAPTER VI-6 COMBINATIONAL LOGIC MULTIPLEXERS DESIGN WITH MULTIPLEXERS ENCODERS MULTIPLEXERS -BASIC MULTIPLEXER -USING PASS GATES Any Boolean function can be implemented by setting the inputs corresponding to the function and the selectors as the variables. Example: Module Enable X Y Z F E x Multiplexer S 2 S X Y S Z f R.M. Dansereau; v..

52 Copyright 2, 23 MD Ciletti 69 BUILDING BLOCKS: MULTIPLEXERS (p 6) MUXES PROVIDE STEERING FOR DATAPATHS. a sel y_out b y_out = sel. a + sel'. b

53 Copyright 2, 23 MD Ciletti 7 DEMULTIPLEXERS A demultiplexer has a single datapath input, n datapath outputs, and m address inputs. The m-bit address determines which of the n outputs is connected to the input. Address[m-: ] m Address Data_Out [n-] Data_In Data_In Demultiplexer Data_Out [] Output channel selection: Data_Out [n-: ] = Data_In [Address[k]]

54 Copyright 2, 23 MD Ciletti 72 ENCODERS An encoder has n inputs and m outputs, with n = 2 m. Ordinarily, only one of the inputs is asserted at a time. A unique output bit pattern (code) is assigned to each of the n inputs. The asserted output is determined by the index of the asserted bit of the n-bit binary input word. Data_In[n-] Data_In n Data_Out m Data_Out m Encoder Data_In[] Encoder Example: n = 4, m = 2, Data_In [3] = and Data_In [k] = for < k < n, k 3 Data_Out [:] = 2 = 3 A Mux does not change the data input, but encoders transform the data input to form the data output. The encoder assigns a unique bit pattern to each input line.

55 Copyright 2, 23 MD Ciletti 73 PRIORITY ENCODERS A priority encoder allows multiple input bits to be asserted simultaneously, and uses a priority rule to form an output bit pattern. Example: Data_In [3:] Data_out [2:] xxx xxxx xx xxxx x xxxx xxxx xxx xx x Note: "-" denotes a don't care condition.

56 Copyright 2, 23 MD Ciletti 74 DECODERS A decoder has m inputs and n outputs, with n = 2 m. Only one of the outputs is asserted at a time. The asserted output is determined by the decimal equivalent of the m-bit binary input word. Data_Out[n-] Data_In Data_out Data_In m n m Decoder Decoder Data_Out[] Example: n = 4, m = 2 Data_In = 2 and Data_Out [3] = and Data_Out[k] = for k 3

57 CHAPTER VI-6 COMBINATIONAL LOGIC DECODERS IMPLEMENTATION DECODERS -BASIC DECODER -WITH ENABLE -TRUTH TABLES How can a decoder be implemented? Fill in the circuit! A 2 A A D 7 D 6 D 5 D 4 D 3 D 2 D D A 2 A A A 2 A A A 2 A A A 2 A A A 2 A A A 2 A A A 2 A A A 2 A A R.M. Dansereau; v..

58 CHAPTER VI-7 COMBINATIONAL LOGIC DECODERS DESIGNING WITH DECODERS DECODERS -WITH ENABLE -TRUTH TABLES -IMPLEMENTATION Any Boolean function can implemented using a decoder and OR gates by ORing together the function s minterms. A 2 Inputs A A Outputs F F 2 A 2 2 A A F to-8 Decoder F R.M. Dansereau; v..

59 CHAPTER VI-8 COMBINATIONAL LOGIC DECODERS DECODER NETWORKS DECODERS -TRUTH TABLES -IMPLEMENTATION -DESIGNING W/DECODERS We can also use multiple decoders to form a larger decoder. 3-to-8 Decoder Implemented with two 2-to-4 Decoders A 2 used with enable input to control which decoder will output the. A A A E 2-to-4 Decoder 2 3 D D D 2 D 3 A and A used to select which output on specific decoder will output. 2 2 E 2-to-4 Decoder 2 3 D 4 D 5 D 6 D 7 R.M. Dansereau; v..

60 CHAPTER VI-22 COMBINATIONAL LOGIC ADDERS HALF- AND FULL-ADDERS DEMULTIPLEXERS SHIFTERS ROTATORS -BASIC ROTATOR Two basic building blocks for arithmetic are half- and full-adders as depicted by the block diagrams below. A B A B C OUT Carry-out HA C OUT Carry-out FA C IN Carry-in S Sum S Sum Half-adder Full-adder R.M. Dansereau; v..

61 CHAPTER VI-23 COMBINATIONAL LOGIC ADDERS HALF-ADDER (HA) SHIFTERS ROTATORS ADDERS -HALF- & FULL-ADDERS First of all, how do we add? 2 s complement arithmetic allows us to add numbers normally. Inputs A B Sum Carry-out S = AB+ AB = A B S C OUT A B C OUT = AB S C OUT R.M. Dansereau; v..

62 CHAPTER VI-24 COMBINATIONAL LOGIC ADDERS FULL-ADDER (FA) () ROTATORS ADDERS -HALF- & FULL-ADDERS -HALF-ADDER (HA) Half-adder missed a possible carry-in. A full-adder (FA) includes this additional carry-in. Inputs Carry-in Sum Carry-out A B C IN S C OUT S = ( A B) C IN C OUT = AB + C IN ( A B) R.M. Dansereau; v..

63 CHAPTER VI-25 COMBINATIONAL LOGIC ADDERS FULL-ADDER (FA) (2) ADDERS -HALF- & FULL-ADDERS -HALF-ADDER (HA) -FULL-ADDER (FA) Half-adder S = ( A B) C IN C OUT = AB + C IN ( A B) Half-adder A B S C OUT C IN R.M. Dansereau; v..

64 CHAPTER VI-26 COMBINATIONAL LOGIC ADDERS BINARY ADDITION ADDERS -HALF- & FULL-ADDERS -HALF-ADDER (HA) -FULL-ADDER (FA) A 4-bit binary adder can be formed with four full-adders as follows. A 3 B 3 A 2 B 2 A B A B FA C 3 FA C 2 FA C FA C S 3 S 2 S S C 4 R.M. Dansereau; v..

Chapter 3. Gate-Level Minimization. Outlines

Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to

Advanced Digital Design with the Verilog HDL

Copyright 2, 23 MD Ciletti Advanced Digital Design with the Verilog HDL M. D. Ciletti Department of Electrical and Computer Engineering University of Colorado Colorado Springs, Colorado ciletti@vlsic.uccs.edu

Chapter 2. Boolean Expressions:

Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

Combinational Logic & Circuits

Week-I Combinational Logic & Circuits Spring' 232 - Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other

Experiment 4 Boolean Functions Implementation

Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

Gate Level Minimization Map Method

Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically

Boolean Algebra and Logic Gates

Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can

Get Free notes at Module-I One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)

IT 201 Digital System Design Module II Notes

IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.

Specifying logic functions

CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last

Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 2-1 Binary Logic and Gates 2-2 Boolean Algebra 2-3 Standard Forms 2-4 Two-Level Circuit Optimization

Gate-Level Minimization. section instructor: Ufuk Çelikcan

Gate-Level Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to

Chapter 3. Boolean Algebra and Digital Logic

Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how

Review. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/4-04. Seq. Circuit Behavior. Outline.

Review EECS 150 - Components and Design Techniques for Digital Systems Lec 05 Boolean Logic 94-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley Design flow

1. Mark the correct statement(s)

1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another

Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

QUESTION BANK FOR TEST

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make

Chapter 2 Boolean algebra and Logic Gates

Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions

Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

Gate Level Minimization

Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch- Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =

2.6 BOOLEAN FUNCTIONS

2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD

Lecture (05) Boolean Algebra and Logic Gates

Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either

Combinational Logic Circuits

Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don

Code No: 07A3EC03 Set No. 1

Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,

Boolean Algebra. BME208 Logic Circuits Yalçın İŞLER

Boolean Algebra BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 5 Boolean Algebra /2 A set of elements B There exist at least two elements x, y B s. t. x y Binary operators: +

Contents. Chapter 3 Combinational Circuits Page 1 of 34

Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4

R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai

L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai- 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT - I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean

Chapter 2 Combinational Logic Circuits

Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard

Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples

Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples Incompletely specified functions

Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

Unit-IV Boolean Algebra

Unit-IV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of

28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28

Module -7. Karnaugh Maps

1 Module -7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or Sum-of-Minterms (SOM) 2.4 Canonical product of sum or Product-of-Maxterms(POM)

2.1 Binary Logic and Gates

1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary

CS470: Computer Architecture. AMD Quad Core

CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction

www.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL

Experiment 3: Logic Simplification

Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions

INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input

數位系統 Digital Systems 朝陽科技大學資工系. Speaker: Fuw-Yi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷

數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: Fuw-Yi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input

ECE380 Digital Logic

ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8- Terminology For

CMPE223/CMSE222 Digital Logic

CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Terminology For a given term, each

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many

VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201- DIGITAL PRINCIPLE AND SYSTEM DESIGN

UNIT II. Circuit minimization

UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.

Menu. Algebraic Simplification - Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification

Menu Minterms & Maxterms SOP & POS MSOP & MPOS Simplification using the theorems/laws/axioms Look into my... 1 Definitions (Review) Algebraic Simplification - Boolean Algebra Minterms (written as m i ):

SWITCHING THEORY AND LOGIC CIRCUITS

SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented

Chapter 2: Combinational Systems

Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch

Gate-Level Minimization

Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

Combinational Logic Circuits Part III -Theoretical Foundations

Combinational Logic Circuits Part III -Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic

Variable, Complement, and Literal are terms used in Boolean Algebra.

We have met gate logic and combination of gates. Another way of representing gate logic is through Boolean algebra, a way of algebraically representing logic gates. You should have already covered the

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of

VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year 2018 19 III SEMESTER CS8351-DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech

Simplification of Boolean Functions

COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean

COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA

Introduction to synthesis. Logic Synthesis

Introduction to synthesis Lecture 5 Logic Synthesis Logic synthesis operates on boolean equations and produce optimized combinational logic Logic Minimization Two-level logic minimization Two-level logic

10EC33: DIGITAL ELECTRONICS QUESTION BANK

10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function

Gate-Level Minimization

MEC520 디지털공학 Gate-Level Minimization Jee-Hwan Ryu School of Mechanical Engineering Gate-Level Minimization-The Map Method Truth table is unique Many different algebraic expression Boolean expressions may

Midterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil

Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final

Announcements. Chapter 2 - Part 1 1

Announcements If you haven t shown the grader your proof of prerequisite, please do so by 11:59 pm on 09/05/2018 (Wednesday). I will drop students that do not show us the prerequisite proof after this

X Y Z F=X+Y+Z

This circuit is used to obtain the compliment of a value. If X = 0, then X = 1. The truth table for NOT gate is : X X 0 1 1 0 2. OR gate : The OR gate has two or more input signals but only one output

DKT 122/3 DIGITAL SYSTEM 1

Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits

Injntu.com Injntu.com Injntu.com R16

1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

Literal Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10

Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm

Combinational Circuits

Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables

Binary logic. Dr.Abu-Arqoub

Binary logic Binary logic deals with variables like (a, b, c,, x, y) that take on two discrete values (, ) and with operations that assume logic meaning ( AND, OR, NOT) Truth table is a table of all possible

Computer Science. Unit-4: Introduction to Boolean Algebra

Unit-4: Introduction to Boolean Algebra Learning Objective At the end of the chapter students will: Learn Fundamental concepts and basic laws of Boolean algebra. Learn about Boolean expression and will

R10. II B. Tech I Semester, Supplementary Examinations, May

SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map

Karnaugh Map (K-Map) Ch. 2.4 Ch. 2.5 Simplification using K-map A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or

Gate-Level Minimization

Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

UNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.

UNIT-4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?

CS February 17

Discrete Mathematics CS 26 February 7 Equal Boolean Functions Two Boolean functions F and G of degree n are equal iff for all (x n,..x n ) B, F (x,..x n ) = G (x,..x n ) Example: F(x,y,z) = x(y+z), G(x,y,z)

Digital Logic Lecture 7 Gate Level Minimization

Digital Logic Lecture 7 Gate Level Minimization By Ghada Al-Mashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. K-map principles. Simplification using K-maps. Don t-care

Chapter 6. Logic Design Optimization Chapter 6

Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Two-level Optimization Manipulating a function until it is

Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide

Chapter 2 Combinational

Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic

Points Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map

Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions Sum-of-Products (SOP),

Digital logic fundamentals. Question Bank. Unit I

Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative

Chapter 3 Simplification of Boolean functions

3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean

DIGITAL CIRCUIT LOGIC UNIT 7: MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES

DIGITAL CIRCUIT LOGIC UNIT 7: MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES 1 iclicker Question 13 Considering the K-Map, f can be simplified as (2 minutes): A) f = b c + a b c B) f = ab d + a b d AB CD

(Refer Slide Time 6:48)

Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture - 8 Karnaugh Map Minimization using Maxterms We have been taking about

END-TERM EXAMINATION

(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map

CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,

Hours / 100 Marks Seat No.

17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)

1/28/2013. Synthesis. The Y-diagram Revisited. Structural Behavioral. More abstract designs Physical. CAD for VLSI 2

Synthesis The Y-diagram Revisited Structural Behavioral More abstract designs Physical CAD for VLSI 2 1 Structural Synthesis Behavioral Physical CAD for VLSI 3 Structural Processor Memory Bus Behavioral

Gate-Level Minimization

Gate-Level Minimization Mano & Ciletti Chapter 3 By Suleyman TOSUN Ankara University Outline Intro to Gate-Level Minimization The Map Method 2-3-4-5 variable map methods Product-of-Sums Method Don t care

Outcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps

.. Outcomes Unit I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate size and contents of a memory to implement any logic function (i.e. truth

Simplification of Boolean Functions

Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.