On-Line Error Detecting Constant Delay Adder

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1 On-Line Error Detecting Constant Delay Adder Whitney J. Townsend and Jacob A. Abraham Computer Engineering Research Center The University of Texas at Austin whitney and Parag K. Lala Computer Science and Computer Engineering University of Arkansas Abstract Fault tolerance requires the inclusion of redundant information. In this paper an on-line error detecting adder is presented in which the redundant information serves a dual purpose. It provides fault tolerance during the arithmetic operations while also providing a method by which addition is constrained to become a constant delay operation regardless of the word size of the operands. 1. Introduction Fault tolerance in digital circuits is achieved by the inclusion within a circuit of either hardware redundancy, information redundancy, or time redundancy [4]. Information redundancy requires the use of extra bits which are used to encode the information in such a way that the presence of errors can be detected and possibly corrected. There are numerous codes which have been presented in the literature as a means of achieving error detection capabilities including parity codes, Hamming code, Berger code, and many others [5]. Addition is a fundamental operation in all digital computations. Error detecting adders have been studied previously in [8]. This paper describes the design of an adder which features both on-line error detection capabilities employing information redundancy techniques and also provides a method constraining addition to become a constant delay operation regardless of the word size of the operands. The adder achieves these twin objectives by using ideas from signed digit number representations therefore achieving constant adder delay. However rather than encoding the signed digits with a minimum number of bits, the signed This material is based in part upon work supported under a National Science Foundation Graduate Research Fellowship and in part by Subcontract No. SA3271JB from the University of California at Berkeley under prime Contract 98-DT-660 from the Microelectronic Advanced Research Corporation MARCO). digits are encoded by a -out-of- code facilitating the online error detection [12]. The constant delay adder design considered here was first proposed in [13]. The contribution of the current paper includes optimized encoding and decoding methods. More importantly, the formation of both the intermediate sum and carry as well as the final sum are now divided into two versions. The first is a streamlined version applicable for newly converted operands while the second is a more complex version required for ongoing operands. Additionally the first version is further subdivided and optimized to take advantage of knowledge regarding just converted operands. The organization of this paper is as follows. Part 2 provides background information relating to the fault tolerance technique of information redundancy through numerical encoding and to the arithmetic of signed digit numbers. Part 3 presents the methodology used in the design of this adder, highlighted by a two operand addition example. Part 4 describes use of this adder for multi-operand addition and illustrates it by a three operand example. Part 5 provides conclusions and highlights future possible implementations of interest for this design. 2. Background This section provides a brief discussion of the use of numerical encoding for information redundancy. This is followed by a review of constant delay arithmetic using signed digit numbers Numerical encoding Numerical encoding has been well studied as a means of achieving information redundancy. One code used for this purpose is an -out-of- code as described in [4, 5]. An -out-of- code is a code of length which has number of in each code word. Single bit errors are detectable using -out-of- codes because they are revealed by the presence of a noncode word that contains or. Self-checking circuits using -out-of- codes 1

2 Addend Augend 1 out of 3 encoding 1 out of 3 encoding Intermediate Sum Carry Final Sum Decoder Sum Figure 1. Block diagram for two operand addition are described in [1]. A more recent survey of techniques including -out-of- codes is given in [11]. A subset of -out-of- codes are the -out-of- codes, sometimes used as state encodings and known by the term, one-hot encoding. -out-of- codes as the name implies have only a single present in any code word. Checkers for -out-of- codes produce a two-rail code, which is itself a -out-ofcode, as output. If the codeword produced by the checking circuit becomes either 00 or 11 then an error has occurred either within the adder or within the checking circuit Constant delay arithmetic Constant delay arithmetic is possible using number representations which permit addition to become a parallel operation. Common number systems, such as the two s complement representation or the decimal number system, have digit sets in which the cardinality of the digit set is equal to the value of the radix. This allows each number representation to be canonical. Redundant number systems, such as the signed digit numbers in which each digit carries its own sign, have digit sets that contain more digits than the value of the radix. In such a system a number can have more than one representation. The first redundant signed digit number representations which were proposed used radices of greater than two [2]. In these systems, each digit with the exception of zero is present in both positive and negative polarities. A line drawn above a digit indicates that the digit is a negative digit. In systems with radices greater than two, constant delay arithmetic is implemented by restricting the digit set implementing the intermediate sum and carry to a subset such that a carry can never occur when the final sum is computed. The digit set for signed binary number representations are composed of the following digit set,. Unlike the signed digit number systems with larger radices however, it is not possible to use only a subset of the digits to compose the intermediate sum and carry [9]. Thus to compute the intermediate sum and carry, the digits in the next lower position must also be considered so that a or a which could produce a carry can never occur in the final sum generation. When the intermediate sum and carry digits are constructed for two operands, care must be taken so that a carry is not created in the final sum. Only one digit must be considered from the next lower bit position of the augend. If a single is present in a column to be added then the next lower augend bit must also be considered and the in the column of interest encoded as either a carry of and an intermediate sum of if a is present in the next lower augend bit yielding. Conversely the must be encoded as a carry of and an intermediate sum of if the next lower augend bit is not a. A table is typically constructed defining all possible combinations which may occur. Several different table encodings are possible. 3. Two operand addition Figure 1 illustrates the block diagram of the constant delay adder for two operand addition. The adder design uses a -out-of- code whose three valid code words come from the following set,. The use of this encoding allows the detection of transient and static faults including stuck-at, stuck-open, and bridging faults. This section discusses each block of the diagram as well as the -out-of- checkers which provide the fault detection Operand encoding Although this adder circuit employs the theory of signed binary digits, each digit is encoded by a -out-of- code word. This is in contrast to the usage of this encoding for signed binary digits in [6] in which the digits were first encoded into a signed binary digit representation and then further transformed into the -out-of- code words. For the current encoding method, is represented by the code word,, is represented by the code word,, and is represented by the remaining code word,. This encoding method is equally applicable to numbers represented in either two s complement or signed magnitude number representations. In the following example, is added to. The operands are described first by decimal number representations, then by two s complement representations, and 2

3 % * % * finally by the corresponding -out-of- encoding. This is followed by the radix polynomial representations that show how the value can be obtained from the -out-of- code words for both the addend and the augend respectively. Previously in [13], two XOR gates were required to encode each bit of the operands. This is now optimized to require only a single inverter to encode each bit of the operands. This is made possible by recognizing that the Most Significant Bit MSB) of each operand will always be encoded from the subset and that the remaining bits of the operands will always be encoded from the subset. The same circuit can be used to encode both the MSB bits. This circuit is shown in Fig- and the remaining ure 2 wired for the remaining bits. In this figure the three wires representing the -out-of- encoding are labeled,, and! respectively. Because the bits will be encoded from the set these bits will never be encoded as. Therefore the line can be tied low. When this circuit is used to encode the MSB, the and! connections are reversed, with the! line being tied low and the line driven by the MSB. H Bit M Figure 2. Encoding for L bits 3.2. Intermediate sum and carry digit formation Once the addend and the augend have been converted into code words, the addition begins with the formation of the intermediate sum and carry digits. Each of the code words representing the original digits are added together. Two tables are used to define this process, one table for the MSB code word digits and another table for the remaining code word digits. The table defining the lower bits is shown first in Table 1. Due to the restriction that these bits will always be encoded from the subset only four additions are possible: #" #" $" and. The intermediate sum digits are restricted to the subset of and similarly the carry digits are restricted to the subset of. This ensures that the two restricted additions, and, will never occur in the final sum. Restricting the table entries from the full set of nine possibilities to these four entries simplifies the circuit implementation. Figure 3 shows the circuit representation for the lower code word digits. Since will never occur as a code word digit of either operand, % and % are not represented as inputs to the circuit. Similarly, a carry of will also never occur, thus is not present in the circuit schematic. Finally, to ensure that a will never occur in computing the final sum, and are encoded using a carry of and an intermediate sum of thus. Since the output of these four additions can never produce a as an intermediate sum digit, ' is not represented in the circuit schematic either. Because it is known that only this subset of digits will appear as operand digits in these positions the next lower bit of the augend need not be considered here. Similarly, Table 2 defines the process of forming the intermediate sum and carry digits for the MSB of the addend and augend. The only possible digit operands are those from the MSB subset of and only four additions possible for the MSB: $" #" ; and. The intermediate sum digits produced by this circuit are restricted to the same subset as before,, while the carry digits produced are from the subset,. As during the encoding, the same circuit shown in Figure 3 can be utilized for the MSB code word digits by employing a different wiring scheme as shown in Figure 4. Since will never occur as a digit of either operand, ) * and * are not represented as inputs to the circuit. Similarly, a carry of will also never occur, thus is not present. Because can never occur as an intermediate sum digit, ' is also omitted from the circuit schematic. The following example uses both Table 1 and Table 2 to produce the appropriate intermediate sum and carry digits. 3

4 intermediate sum carry digits Addend Augend Carry Intermediate Sum Table 1. Table 2. MSB intermediate sum carry digits Addend Augend Carry Intermediate Sum AddM AugM AddL AugL AddH AugH AddM AugM C L C H C M C M IS M IS M IS H IS H Figure 3. Circuit for the intermediate sum carry digits Figure 4. Circuit for the MSB intermediate sum carry digits ' 3.3. Final sum generation The final sum is formed from the intermediate sum and the carry digits. This addition is now carry-free due to the restrictions placed on the previous tables defining the assignment of the intermediate sum and carry digits. Table 3 contains the five possible additions for the final sum. Although there are nine possible additions, two are already excluded, and. Two other possibilities are excluded because the intermediate sum digits have been restricted in all cases to the subset,. Thus there are no entries in Table 3 for an addend code word digit,, because that code word digit will never occur as an addend digit. The computation of the final sum for the example is continued using Table 3. The leftmost code word represents the carry out from the addition and the resulting sum is present in the remaining four code words. ' 3.4. Decoding The final step is to convert the encoded digits back into either two s complement or signed magnitude number representation. In [13] this was accomplished by creating two Table 3. Final sum digit Addend Augend Final Sum

5 * % * words, one positive and one negative, and then subtracting the negative word from the positive to obtain the decoded result. The current methodology produces two operands that only require addition to complete the operation. First a positive word is formed in which all code word digits,, are represented by and all the remaining code word digits, and, are represented by. This is done by examining. Next a complemented negative word is formed directly. This permits an addition operation with a carry in of to be substituted for the previously required subtraction. In this complemented negative word all code word digits,, are represented by and all the remaining code word digits, and are represented by. This requires a single inverter for each code word digit,. The ongoing two operand example concludes with the addition of the positive and complemented negative words which are formed from the final sum in the previous section. The addition of and produces a sum of ) and a carry out of as shown out-of-3 checkers ' -out-of- checker circuits are used to detect errors in the code words. If any code word contains more than one or less than one an error has occured. These circuits are used either concurrently with the decoding to check the final sum or concurrently with the production of the final sum if earlier detection of the intermediate sum and carry is desirable. -out-of- checkers are described in [3, 7, 10, 14]. 4. Multi-operand addition The previous section described a two operand addition performed by the constant delay adder. However the constant delay adder should only be implemented to perform multi-operand addition due to the decoding penalty which requires the use of a traditional adder. Multi-operand addition is used in many circuit designs including multiplication, division, digital signal processing applications, and CORDIC applications. In this section a multi-operand example and the required extensions to the tables described previously are presented. In the preceding sections knowledge about recently converted operands was used to simplify the defining tables and the corresponding circuits by separating the MSB from the remaining bits. In an ongoing addition any digit from Table 4. Ongoing intermediate sum carry digits Addend Augend Bit Carry Intermediate Sum dc dc dc dc dc dc dc Table 5. Ongoing final sum Addend Augend Final Sum the entire digit set may now be present in any position in either the addend or the augend. Therefore, only one table is needed to define the ongoing intermediate sum and carry digits. However, the first addition can still be completed using the previously defined tables and it is only with the introduction of the additional operands that the following more complex tables must be considered. Table 4 defines all of the nine possibilities for the addend and augend digits. The next lower bit position of the augend must also be considered as it was in the signed binary digit respresentation described in Section 2.2. This lower augend bit position is represented in Table 4 by the column labeled Bit. It is possible to check the value of this code word digit by only considering. Combinations in which the presence or the absence of a in the next lower bit of the augend have no effect on the encoding of the intermediate sum and carry digits are indicated by, representing don t care, in the Bit column. Table 5 defines the ongoing final sum that also requires additional entries. Since any digit in the ongoing operands can be represented by any code word, seven entries of the nine that are possible, are required in Table 5. The only two possibilities that can be excluded are the two that would permit a carry, and, because Table 4 ensures 5

6 that these combinations will not occur. In the following example is added to using both Table 1 and Table 2. The intermediate final sum of and is computed using Table 3. Next the third operand, is added using Table 4. The final sum of the second computation is computed using Table 5. ' ' 5. Conclusions This paper has described a design for an on-line error detecting constant delay adder. Optimized encoding and decoding methods have been shown that benefit from the simplicity of the -out-of- encoding. This encoding is used to represent the digits of the addend and the augend as signed binary numbers. Formation of both the intermediate sum and the carry digits as well as the final sum digits have been divided into two versions. The first is a streamlined version applicable for newly converted operands and the second is a more complex version required for the addition of ongoing operands. The first version has been further subdivided and optimized by separately considering the MSB of the operands during both the encoding and the formation of the intermediate sum and carry word digits. The constant delay adder provides an extremely fast error detecting adder. While error detection can be provided by -out-of- checking circuits throughout most stages of the addition, errors are not detected during the decoding. Error detection during this stage must be provided by alternative methods. Although a two operand addition was presented to illustrate the functionality of the constant delay adder, the adder must be realized in operations requiring multi-operand addition due to the requirement for a traditional adder during decoding. Future work includes implementing this adder into circuits requiring multi-operand addition and comparing the results with those obtained from extremely fast traditional adders such as parallel prefix adders or traditional signed binary digit circuits. References [1] D. A. Anderson and G. Metze. Design of totally selfchecking check circuits for m-out-of-n codes. IEEE Trans. On Computers, C223): , March [2] A. Avizienis. Signed-digit number representations for fast parallel arithmetic. IRE Trans. Electronic Computers, 109): , September [3] P. Golan. Design of totally self-checking checker for 1-outof-3 code. IEEE Trans. on Computers, C333):285, March [4] B. W. Johnson. Design and Analysis of Fault-Tolerant Digital Systems. Addison-Wesley Publishing Company, [5] P. K. Lala. Self-Checking and Fault-Tolerant Digital Design. Morgan Kaufmann Publishers, [6] P. K. Lala and A. Walker. On-line error detectable carry-free adder design. In IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 66 71, October 24-26, [7] J.-C. Lo and S. Thanawastien. On the design of combinational totally self-checking 1-out-of-3 code checkers. IEEE Trans. on Computers, 393): , March [8] M. Nicolaidis. Efficient implementations of self-checking adders and ALUs. In 23rd International Symposium on Fault-Tolerant Computing, pages , [9] B. Parhami. Generalized signed-digit number systems: A unifying framework for redundant number representations. IEEE Trans. on Computers, 39. [10] A. M. Paschalis, C. Efstathiou, and C. Halatsis. An efficient TSC 1-out-of-3 code checker. IEEE Trans. on Computers, 393): , March [11] S. J. Piestrak. Self-checking design in eastern Europe. IEEE Design Test of Computers, 13:16 25, Spring [12] N. Takagi and S. Yajima. On-line error-detectable highspeed multiplier using redundant binary representation and three-rail logic. IEEE Trans. on Computers, C3611): , November [13] W. J. Townsend, M. A. Thornton, and P. K. Lala. On-line error detection in a carry-free adder. In 11th IEEE/ACM International Workshop on Logic Synthesis, pages , June 4-7, Unpublished workshop proceedings available at whitney/pubs.html. [14] J. Q. Wang and P. K. Lala. Partially strongly fault secure and partially strongly code disjoint 1-out-of-3 code checker. IEEE Trans. on Computers, C4310): , October

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