Computer Organization

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1 Slide 4-1 Computer Organization Stored Program Computers and Electronic Devices Slide 4-2 Pattern Jacquard Loom Variable Program Fixed Electronic Device Stored Program Device 1

2 Program Specification Slide 4-3 Source int a, b, c, d;... a = b + c; d = a - 100; Assembly Language ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a load R4,=100 subtract R3,R4 store R3,d Machine Language Slide 4-4 Assembly Language ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a load R4,=100 subtract R3,R4 store R3,d Machine Language

3 The von Neumann Architecture Slide 4-5 Central Processing Unit (CPU) Arithmetical Logical Unit (ALU) Control Unit (CU) Address Bus Data Bus Primary Memory Unit (Executable Memory) Device The ALU Slide 4-6 R1 R2... Rn Right Operand Left Operand Result Functional Unit load R3,b load R4,c add R3,R4 store R3,a Status Registers To/from Primary Memory 3

Control Unit Slide 4-7 load R3,b load R4,c add R3,R4 store R3,a Fetch Unit Decode Unit Execute Unit PC IR 3050 load R4, c 3046 3050 3054 3058 101110010011001 101110010100000 101001110011000

4 Control Unit Slide 4-7 load R3,b load R4,c add R3,R4 store R3,a Fetch Unit Decode Unit Execute Unit PC IR 3050 load R4, c Control Unit Primary Memory Control Unit Operation Slide 4-8 Fetch phase: Instruction retrieved from memory Execute phase: ALU op, memory data reference, I/O, etc. PC = <machine start address>; IR = memory[pc]; haltflag = CLEAR; while(haltflag not SET) { execute(ir); PC = PC + sizeof(instruct); IR = memory[pc]; // fetch phase }; 4

Primary Memory Unit Slide 4-9 MAR MDR Command 1234 98765 read 0 1 2 Read Op: 1. Load MAR with address 2. Load Command with read 3.

5 Primary Memory Unit Slide 4-9 MAR MDR Command read Read Op: 1. Load MAR with address 2. Load Command with read 3. Data will then appear in the MDR n-1 The Device-Controller-Software Relationship Slide 4-10 Software in the CPU Application Program Abstract I/O Machine Device manager Program to manage device controller Supervisor mode software Device Controller Device 5

6 Device Controller Interface Busy/done bits used to signal event occurrences to software and software to device Slide busy done Error code... busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined) Command Status Data 0 Data 1 Logic Data n-1 Performing a Write Operation Slide 4-12 while(deviceno.busy deviceno.done) <waiting>; deviceno.data[0] = <value to write> deviceno.command = WRITE; while(deviceno.busy) <waiting>; deviceno.done = TRUE; Devices much slower than CPU CPU waits while device operates Would like to multiplex CPU to a different process while I/O is in process 6

7 CPU-I/O Overlap Slide 4-13 Ready Processes Ready Processes Ready Processes CPU CPU CPU Device Device I/O Operation Device Uses CPU Determining When I/O is Complete Slide 4-14 CPU Interrupt Pending Device Device Device CPU incorporates an interrupt pending flag When device.busy FALSE, interrupt pending flag is set Hardware tells OS that the interrupt occurred Interrupt handler part of the OS makes process ready to run 7

8 Control Unit with Interrupt (Hardware) Slide 4-15 PC = <machine start address>; IR = memory[pc]; haltflag = CLEAR; while(haltflag not SET) { execute(ir); PC = PC + sizeof(instruct); IR = memory[pc]; if(interruptrequest) { memory[0] = PC; PC = memory[1] }; memory[1] contains the address of the interrupt handler Interrupt Handler (Software) Slide 4-16 interrupthandler() { saveprocessorstate(); for(i=0; i<numberofdevices; i++) if(device[i].done) goto devicehandler(i); /* something wrong if we get to here */ devicehandler(int i) { finishoperation(); returntoscheduler(); } 8

9 A Race Condition Slide 4-17 What happens if a second interrupt comes in the middle saveprocessorstate() { of the first? for(i=0; i<numberofregisters; i++) memory[k+i] = R[i]; for(i=0; i<numberofstatusregisters; i++) memory[k+numberofregisters+i] = StatusRegister[i]; } PC = <machine start address>; Block other interrupt IR = memory[pc]; while processing first haltflag = CLEAR; while(haltflag not SET) { execute(ir); PC = PC + sizeof(instruct); IR = memory[pc]; if(interruptrequest && InterruptEnabled) { disableinterupts(); memory[0] = PC; PC = memory[1] }; Revisiting the trap Instruction (Hardware) Slide 4-18 executetrap(argument) { setmode(supervisor); switch(argument) { case 1: PC = memory[1001]; // Trap handler 1 case 2: PC = memory[1002]; // Trap handler 2... case n: PC = memory[1000+n];// Trap handler n }; The trap instruction dispatches a trap handler routine atomically Trap handler performs desired processing A trap is a software interrupt 9

10 Direct Memory Access Slide 4-19 Primary Memory Primary Memory CPU CPU Controller Controller Device Device Addressing Devices Slide 4-20 copy-in R3, 0x012, 4 Load R3, 0xFFFF0124 Device Addresses Memory Addresses Primary Memory Device 0 Device 1 Device n-1 Memory Addresses Primary Memory Device 0 Device 1 Device n-1 10

11 Software Polling I/O // Start the device While((busy == 1) (done == 1)) wait(); // Device I/O complete done = 0; Slide 4-21 busy done Hardware while((busy == 0) && (done == 1)) wait(); // Do the I/O operation busy = 1; Fetch-Execute Cycle with an Interrupt Slide 4-22 while (haltflag not set during execution) { IR = memory[pc]; PC = PC + 1; execute(ir); if (InterruptRequest) { /* Interrupt the current process */ /* Save the current PC in address 0 */ memory[0] = PC; /* Branch indirect through address 1 */ PC = memory[1]; } } 11

12 Detecting an Interrupt Slide 4-23 CPU InterruptRequest flag Device Device Device The Interrupt Handler Slide 4-24 Interrupt_Handler{ saveprocessorstate(); for (i=0; i<number_of_devices; i++) if (device[i].done == 1) goto device_handler(i); /* Something wrong if we get here */ } 12

13 Disabling Interrupts Slide 4-25 if(interruptrequest && InterruptEnabled) { /* Interrupt current process */ disableinterrupts(); memory[0] = PC; PC = memory[1]; } The Trap Instruction Operation Slide 4-26 trap 1 Mode S 2 Branch Table 3 Trusted Code User Supervisor 13

Intel System Initialization Slide 4-27 RAM Boot Prog Power Up ROM POST Loader Boot Device CMOS BIOS OS Hardware Process Data Flow Bootstrapping

14 Intel System Initialization Slide 4-27 RAM Boot Prog Power Up ROM POST Loader Boot Device CMOS BIOS OS Hardware Process Data Flow Bootstrapping Slide 4-28 Bootstrap loader ( boot sector ) 1 BIOS loader 0x x Fetch Unit Decode Unit Execute Unit PC IR Primary Memory 14

15 Bootstrapping Slide 4-29 Bootstrap loader ( boot sector ) 1 2 BIOS loader 0x x Fetch Unit Loader 0x Decode Unit Execute Unit PC IR Primary Memory Bootstrapping Slide 4-30 Bootstrap loader ( boot sector ) 1 2 BIOS loader 0x x Fetch Unit Decode Unit Execute Unit PC IR Loader OS Primary Memory 0x x000A000 15

16 Bootstrapping Slide 4-31 Bootstrap loader ( boot sector ) 1 2 BIOS loader 0x x Fetch Unit Decode Unit Execute Unit PC IR 000A000 3 Loader OS Primary Memory 0x x000A Initialize hardware 5. Create user environment 6. A Bootstrap Loader Program Slide 4-32 FIXED_LOC: // Bootstrap loader entry point load R1, =0 load R2, =LENGTH_OF_TARGET // The next instruction is really more like // a procedure call than a machine instruction // It copies a block from FIXED_DISK_ADDRESS // to BUFFER_ADDRESS read BOOT_DISK, BUFFER_ADDRESS loop: load R3, [BUFFER_ADDRESS, R1] store R3, [FIXED_DEST, R1] incr R1 bleq R1, R2, loop br FIXED_DEST 16

17 A Pipelined Function Unit Slide 4-33 Operand 1 Operand 2 Function Unit Result (a) Monolithic Unit Operand 1 Operand 2 Result (b) Pipelined Unit A SIMD Machine Slide 4-34 ALU Control Unit (a) Conventional Architecture ALU Control Unit ALU ALU ALU (b) SIMD Architecture 17

Slide 5-1. Device. Management. Operating Systems: A Modern Perspective, Chapter 5. Copyright 2004 Pearson Education, Inc.

Slide 5-1. Device. Management. Operating Systems: A Modern Perspective, Chapter 5. Copyright 2004 Pearson Education, Inc. Slide 5-1 Device 5 Management Announcements Slide 5-2 Homework Set #1 due Thursday 11 am, see moodle copyright issues with lectures Program Assignment #1 coming soon Read chapters 4 and 5 skip sections