New Embedded NVM architectures

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1 New Embedded NVM architectures for Secure & Low Power Microcontrollers Jean DEVIN, Bruno LECONTE Microcontrollers, Memories & Smartcard Group STMicroelectronics 11 th LETI Annual review, June 24th, 2009 Grenoble, France

2 New Embedded NVM Architectures Outline MCU Market Current NVM & e-nvm technologies Use of NVM memories in MCUs & Smart-Cards A new architecture, the NOR ETOX page e-flash E-NVM for Low Power E-NVM for read performance E-NVM quality & robustness 2

3 MCU Market 3

4 E-NVM in MCU products e-nvm is a must for Microcontrollers & Smart-Cards products In 2007, Flash-MCUs accounted for more than 30% of the MCU market and are predicted to make up more than 50% of the market by [ ] Embedded Flash technologies play a crucial role in developing reliable, high performance MCUs that are used in various applications including the automotive segment source : Semiconductor Insights 4

5 Current NVM Leading Technologies in Standard Products Leading technologies were adopted because of application features & cost for Code Storage, the ETOX NOR Flash offers fast random access time (few tens of ns) and good density while for Data Storage the NAND cost per bit is unbeatable (Giga Byte range) EEPROM has been adopted for Parameters update (Byte level, few ms) In some case (ex. mobile phone), the software emulation is used to store parameters in the code NOR flash. The data is updated in a next topological location, saving the previous location erase Data update D i FF D i Addr D i+1 SW emulation principle FF 5

6 Current NVM Leading Technologies in Embedded Products E-NVM has been naturally derived from stand-alone memories Both e-flash & e-eeprom are proposed EEPROM is usually associated to a ROM for the application code storage However The e-nand is not yet proposed (design & process integration complexity) Cost effective integration with CMOS logic is crucial. High Voltage need makes the process more complex Foundry Split Gate is widely adopted at.18um node for MCUs, suited for low to medium memory size, but shrink is difficult Flash ETOX NOR EEPROM 2T Split-Gate 6

7 Current NVM Technologies in Embedded Products (con t) More Moore trend First e-flash 90nm has been introduced by ST (Jan, 2008), based on conventional NOR. 2 others suppliers have then announced 90nm e-nvm 65nm e-nvm currently developed by few leaders, including ST A lot of new approaches: Ferroelectric, MRAM, PCM Driven by performance & cost (integration, scalability) Only few are in volume production for generic applications Industrialization issues, quality & robustness are the main obstacles for the pervasion in the market...but winner concepts will give a strong competitive advantage e-pcm 7

8 Low end MCUs General Purposes Microcontrollers e-nvm key features Low power design / process (battery supplied) & low cost implementations ROM+EEPROM & Split Gate are commonly used High End MCUs SRAM Analo g 32bit Core plus a lot of peripherals advanced CMOS is needed e-nvm has to meet high performance requirements Fast access time (20-40ns), critical for Automotive High density (up to few MByte) Used mainly for Code execution, Parameters are stored in external EEPROM or in the e-flash (SW emulation) e-flash preferred choice for flexibility & cost Logic FLASH High-End MCU 8

9 Smart-Cards e-nvm key features Telecom (SIM) Low end MCUs large NVM trend (new added value services) Cost driven market E-Flash replaces ROM flexibility & memory size optimization Power consumption (ETSI norm compliance) Banking, ID, transport Similar to SIM cards but more security features & smaller NVM size RF interface requires low power Security features : anti-tearing, robustness vs attacks (SPA, DPA, laser, ), the e-nvm is involved Secure MCU NAND ROM Analog Logic FLASH SIM Card MCU SRAM Pay TV, IT, Security Highest complexity, medium to large NVM density High number of write cycles (crypto keys) Even more security features (off line system hacking) 9

10 Summary of e-nvm key points vs utilization Size Write Cycles Key points Examples Code execution Large No or few updates (patches, rework,..) 1K- 10K - Cost effectiveness - Data Retention - Fast access time - Factory programming time - Assembly / Soldering reflow (*) OS, application software Executable routines, Data Medium Medium, 10K - In situ write - Write time - Erase Flexibility System files, Java applets in SIM cards Parameters Small High to intensive 100K -1M - SW vs HW emulation - Anti-tearing management - Write current in RF mode - ECC (EEPROM) Counters, Semaphores, Crypto keys, Phone rooming (*) MCUs reflow : 260C few sec (die level), MCUs DAF fast-cure 200C few min. Smart Cards Modules : 175C 5hrs (molding polym.) 160C 3min. (dam & fill die attach) 120C 3hrs (potting polym.) 10

11 e-nvm erase granularity, page flash concept Mixed Code & Parameter storage effective solution E-EEPROM is not cost competitive for high density (few 100K Byte) SW emulation in sector erase flash requires large extra memory & dedicated features (erase suspend, read-while-write) Key points for the implementation A page is typically a word-line erased separately (typ. 128 or 256 Byte) No area penalty vs sector erase array Page erase operation is fast ( ~3ms) Full flexibility for memory allocation (OS memory manager) Erase stress is cancelled in a transparent way for the user thanks to embedded algorithm Page Flash Erasable Row 11

12 e-nvm erase granularity, page flash concept (con t) Intensive Byte update in Page Flash Byte update is programmed with flags & new address records without page erase up to the bank completion Extra memory saving compared to sector erase SW emulation No long sector erase time (1s) to manage when the data bank is full erase-whilewrite or erase suspend are not mandatory for code execution Number of erase cycles is reduced for the same amount of update key for intensive usage (> Million Cy) Parameters bank D i+6 Addr D i+7 FF D i+2 Addr D i+3 Addr D i+4 Addr D i+5 Addr Intensive Update in Page Flash 12

13 e-nvm for Low Power Flash & EEPROM Write requires HV generation Charge pump efficiency is low so Lower write voltage is key Cell geometry and doping are critical Low write parallelism is a good option for Low Power, as CHE (channel hot electron) is very fast (µs range) Large array (high capacitance) results in high dynamic consumption Dedicated design is critical to cope with new LP targets Applications for LP MCUs Medical (Glucose Meter) Metering (Utility Meter) Mobile Accessories, 3D mouse and remote, gaming, GPS watch, sport equipment, games and toys Alarm systems,security sensors Road tolling 13

14 e-nvm for Read performance Sensing key points Read current is optimized with cell geometries, doping & gate-voltage (in conventional NVM) Deselected cells leakage is critical Bit-Line capacitance impact : the sensing time depends on Cbit_line x d(v) / Icell Array Partitioning in large array Data Buffering Higher Data Bus width is implemented as an accelerator x64 & x128 currently used for 32bits Cores Data Cache SRAM buffer for very fast access Read Power saving 14

15 e-nvm quality & robustness E-NVM requires dedicated qualification trials Pure retention, pure cycling, retention after cycling Typical target for Industrial MCU - 10 years at 105 C after 10K at 105 C Data loss in temperature requires in situ programming (PCM soldering) Read & Write disturbs Prediction Models well proven over 20 years for conventional e-nvm ECC Allows < 1 ppm target in EEPROM Typically 8+4 bits or 32+6bits Not mandatory in Page flash (thicker oxide) New failures modes & screen to be identified for innovative technologies Retention after cycling 15

16 Thank you! Any questions? 16