PACKAGE. Package syntax: PACKAGE identifier IS...item declaration... END PACKAGE [identifier]

Transcription

1 Modular Design

2 PACKAGE Package is a collection of : - Type declaration - Component declaration - Constants declaration - Subprograms (functions or procedures) Package is a separate VHDL code consisting of commonly used items. Package syntax: PACKAGE identifier IS...item declaration... END PACKAGE [identifier]

3 PACKAGE My_package.vhd PACKAGE my_package IS TYPE states IS (reset, idle, on, off); CONSTANTk : integer := 1; CONSTANT rst : std_logic_vector(0 to 7) := ; COMPONENT half_adder PORT(a, b : in bit; sum, carry : out bit); END COMPONENT END my_package;

4 PACKAGE LIBRARY ieee; USE ieee.std_logic_1164.all; include standard library USE work.my_package.all; include package ENTITY my_design IS.. END my_design ARCHITECTURE behavior OF my_design IS.... END behavior;

5 VHDL design units can be reused by mean of hierarchy coding ENTITY Component #1 Component #3 Component #2

6 Components are VHDL design unit (code) that is reused in other codes. COMPONENT DECLARATION Each component is declared in declaration section of Architecture (before statement). COMPONENT component_name IS Port declaration END COMPONENT; Example COMPONENT mynand3 IS PORT( a,b,c : IN STD_LOGIC; x : OUT STD_LOGIC ); END COMPONENT;

7 COMPONENT INSTANTIATION (component usage) Each declared component can be instantiated as many times as needed. Each instantiation should be properly PORT MAPPED PORT MAPPING is the definition of internal connections between inputs, outputs and internal signal of different components and the top level entity within a structurally described system. Port mapping is done in the architecture after the keyword.

8 File inverter.vhd: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY inverter IS PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC); END inverter; ARCHITECTURE inverter OF inverter IS b <= NOT a; END inverter;

9 File nand_2.vhd: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_2 IS PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END nand_2; ARCHITECTURE nand_2 OF nand_2 IS c <= NOT (a AND b); END nand_2;

10 ----- File nand_3.vhd: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_3 IS PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC); END nand_3; ARCHITECTURE nand_3 OF nand_3 IS d <= NOT (a AND b AND c); END nand_3;

11 ----- File project.vhd: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY project IS PORT (a, b, c, d: IN STD_LOGIC; x, y: OUT STD_LOGIC); END project; ARCHITECTURE structural OF project IS COMPONENT inverter IS PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT; COMPONENT nand_2 IS PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END COMPONENT; COMPONENT nand_3 IS PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC); END COMPONENT; SIGNAL w: STD_LOGIC; U1: inverter PORT MAP (b, w); component instantiation U2: nand_2 PORT MAP (a, b, x); U3: nand_3 PORT MAP (w, c, d, y); END structural;

12 w

13 TESTBENCH Testbench is a process of testing VHDL model Testbench usually involves in writing another VHDL module which is used for generating of input signals for VHDL model being tested Testbench (VHDL file) Design under test (VHDL file) Testbench uses concept of COMPONENT

14 AND Gate Model -- library ieee; use ieee.std_logic_1164.all; ENTITY andgate IS port( A, B : in std_logic; F : out std_logic); END andgate; ARCHITECTURE func OF andgate IS F <= A and B; END func; TESTBENCH library ieee; use ieee.std_logic_1164.all; ENTITY andgate_tb IS END andgate_tb; ARCHITECTURE tb OF andgate_tb IS COMPONENT andgate IS PORT( A, B : in std_logic; F : out std_logic); END COMPONENT; signal ina, inb, outf : std_logic; mapping: andgate PORT MAP (ina, inb, outf); PROCESS InA <= '0'; --TEST 1 inb <= '0'; WAIT FOR 15 ns; InA <= '0'; --TEST 2 inb <= '1'; WAIT FOR 15 ns; InA <= '1'; --TEST 3 inb <= '1'; WAIT FOR 15 ns; WAIT; stop testbench -- END PROCESS; END tb;

15 TESTBENCH library ieee; use ieee.std_logic_1164.all; ENTITY dff_tb IS END dff_tb; ARCHITECTURE tb OF dff_tb IS signal T_data_in, T_clock, T_data_out : std_logic; COMPONENT dff IS PORT(d, clk: in std_logic; q: out std_logic); END COMPONENT; U_DFF: dff PORT MAP (T_data_in, T_clock, T_data_out); clock_gen: PROCESS T_clock <= '0'; WAIT FOR 5 ns; T_clock <= '1'; WAIT FOR 5 ns; END PROCESS clock_gen; PROCESS T_data_in <= '1'; -- case 1 WAIT FOR 20 ns; T_data_in <= '0'; -- case 2 WAIT FOR 20 ns; WAIT; -- stop testbench END PROCESS; END tb; D flip flop Testbench