ECE 545 Lecture 8. Data Flow Description of Combinational-Circuit Building Blocks. George Mason University
|
|
|
- Loren Ramsey
- 5 years ago
- Views:
Transcription
1 ECE 545 Lecture 8 Data Flow Description of Combinational-Circuit Building Blocks George Mason University
2 Required reading P. Chu, RTL Hardware Design using VHDL Chapter 7, Combinational Circuit Design: Practice 2
3 Fixed Shifters & Rotators ECE 448 FPGA and ASIC Design with VHDL 3
4 Fixed Logical Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A >> C 4 L A(3) A(2) A() A() A(3) A(2) A() A C 4
5 Fixed Logical Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A >> C 4 L A(3) A(2) A() A() A(3) A(2) A() A C C = '' & A(3 downto ); 5
6 Fixed Arithmetic Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A >> C 4 A A(3) A(2) A() A() A C A(3) A(3) A(2) A() 6
7 Fixed Arithmetic Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A >> C 4 A A(3) A(2) A() A() A C A(3) A(3) A(2) A() C = A(3) & A(3 downto ); 7
8 Fixed Logical Shift Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A << C 4 L A(3) A(2) A() A() A(2) A() A() A C 8
9 Fixed Logical Shift Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A << C 4 L A(3) A(2) A() A() A(2) A() A() C = A(2 downto ) & ''; A C 9
10 Fixed Rotation Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A <<< C 4 A(3) A(2) A() A() A(2) A() A() A(3) A C
11 Fixed Rotation Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A <<< C 4 A(3) A(2) A() A() A(2) A() A() A(3) C = A(2 downto ) & A(3); A C
12 Variable Rotators ECE 448 FPGA and ASIC Design with VHDL 2
13 8-bit Variable Rotator Left A 8 3 B A <<< B C 8 To be covered during one of the future classes 3
14 Multiplexers ECE 448 FPGA and ASIC Design with VHDL 4
15 2-to- Multiplexer s s f w f w w w (a) Graphical symbol (b) Truth table VHDL: 5
16 2-to- Multiplexer s s f w f w w w (a) Graphical symbol (b) Truth table VHDL: f <= w WHEN s = '' ELSE w ; or f <= w WHEN s = ' ELSE w ; 6
17 Cascade of two multiplexers w 3 w 2 y w VHDL: s2 s 7
18 Cascade of two multiplexers w 3 w 2 y w VHDL: s2 s f <= w WHEN s = ' ELSE w2 WHEN s2 = ELSE w3 ; 8
19 4-to- Multiplexer (a) Graphic symbol (b) Truth table s s s s s f w w w 2 w 3 f w w w 2 w 3 9
20 4-to- Multiplexer (a) Graphic symbol (b) Truth table s s s s s f w w w 2 w 3 f w w w 2 w 3 WITH s SELECT f <= w WHEN "", w WHEN "", w2 WHEN "", w3 WHEN OTHERS ; 2
21 Decoders ECE 448 FPGA and ASIC Design with VHDL 2
22 2-to-4 Decoder (b) Graphical symbol (a) Truth table w w y 3 En w w y y y y 3 2 w y 2 y En y y x x 22
23 2-to-4 Decoder (b) Graphical symbol (a) Truth table w w y 3 En w w y 3 y 2 y y w y 2 y En y y x x 23
24 2-to-4 Decoder (b) Graphical symbol (a) Truth table w w y 3 En w w y 3 y 2 y y w y 2 y En y y x x Enw <= En & w ; WITH Enw SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; 24
25 VHDL code for a 2-to-4 Decoder entity LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR( DOWNTO ) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO ) ) ; END dec2to4 ; ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO ) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; END dataflow ; 25
26 Encoders ECE 448 FPGA and ASIC Design with VHDL 26
27 Priority Encoder w w w w 2 w 3 y y z y w 3 w 2 w w y y z
28 Priority Encoder w w w w 2 w 3 y y z y w 3 w 2 w w y y z d d 28
29 Priority Encoder w w w w 2 w 3 y y z y y <= "" WHEN w(3) = '' ELSE "" WHEN w(2) = '' ELSE "" WHEN w() = '' ELSE "" ; w 3 w 2 w w y y z z <= '' WHEN w = "" ELSE '' ; d d 29
30 VHDL code for a Priority Encoder entity LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY priority IS PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; z : OUT STD_LOGIC ) ; END priority ; ARCHITECTURE dataflow OF priority IS BEGIN y <= "" WHEN w(3) = '' ELSE "" WHEN w(2) = '' ELSE "" WHEN w() = '' ELSE "" ; z <= '' WHEN w = "" ELSE '' ; END dataflow ; 3
31 Adders ECE 448 FPGA and ASIC Design with VHDL 3
32 Adder mod X Y S 6 32
33 VHDL code for an Adder mod 2 6 LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder6 IS PORT ( X : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; Y : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; S : OUT STD_LOGIC_VECTOR(5 DOWNTO ) ) ; END adder6 ; ARCHITECTURE dataflow OF adder6 IS BEGIN S <= X + Y ; END dataflow ; 33
34 6-bit Unsigned Adder 6 6 Cout X + S Y Cin 6 34
35 Operations on Unsigned Numbers For operations on unsigned numbers USE ieee.std_logic_unsigned.all and signals of the type STD_LOGIC_VECTOR OR USE ieee.numeric_std.all and signals of the type UNSIGNED and conversion functions: std_logic_vector(), unsigned() 35
36 Signed and Unsigned Types Behave exactly like STD_LOGIC_VECTOR plus, they determine whether a given vector should be treated as a signed or unsigned number. Require USE ieee.numeric_std.all; 36
37 VHDL code for a 6-bit Unsigned Adder LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder6 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; Y : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; S : OUT STD_LOGIC_VECTOR(5 DOWNTO ) ; Cout : OUT STD_LOGIC ) ; END adder6 ; ARCHITECTURE dataflow OF adder6 IS SIGNAL Sum : STD_LOGIC_VECTOR(6 DOWNTO ) ; BEGIN Sum <= ('' & X) + Y + Cin ; S <= Sum(5 DOWNTO ) ; Cout <= Sum(6) ; END dataflow ; 37
38 Addition of Unsigned Numbers () LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.numeric_std.all ; ENTITY adder6 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; Y : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; S : OUT STD_LOGIC_VECTOR(5 DOWNTO ) ; Cout : OUT STD_LOGIC ) ; END adder6 ; 38
39 Addition of Unsigned Numbers (2) ARCHITECTURE dataflow OF adder6 IS SIGNAL Xu : UNSIGNED(5 DOWNTO ); SIGNAL Yu: UNSIGNED(5 DOWNTO ); SIGNAL Su : UNSIGNED(6 DOWNTO ) ; BEGIN Xu <= unsigned(x); Yu <= unsigned(y); Su <= ('' & Xu) + Yu + unsigned('' & Cin) ; S <= std_logic_vector(su(5 DOWNTO )) ; Cout <= Su(6) ; END dataflow ; ECE 448 FPGA and ASIC Design with VHDL 39
40 Addition of Unsigned Numbers (3) ARCHITECTURE dataflow OF adder6 IS signal Sum: STD_LOGIC_VECTOR(6 DOWNTO ) ; BEGIN Sum <= std_logic_vector( unsigned('' & X) + unsigned(y) + unsigned('' & Cin) ) ; S <= Sum(5 downto ); Cout <= Sum(6) ; END dataflow ; 4
41 Operations on Signed Numbers For operations on signed numbers USE ieee.numeric_std.all, signals of the type SIGNED, and conversion functions: std_logic_vector(), signed() OR USE ieee.std_logic_signed.all and signals of the type STD_LOGIC_VECTOR 4
42 Multipliers ECE 448 FPGA and ASIC Design with VHDL 42
43 Unsigned vs. Signed Multiplication Unsigned Signed 5 - x x 5 x x
44 8x8-bit Unsigned Multiplier 8 8 a b * c U 6 44
45 Multiplication of unsigned numbers LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.std_logic_unsigned.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); c : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin c <= a * b; end dataflow; 45
46 8x8-bit Signed Multiplier 8 8 a b * c S 6 46
47 Multiplication of signed numbers LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.std_logic_signed.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); c : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin c <= a * b; end dataflow; 47
48 8x8-bit Unsigned and Signed Multiplier 8 8 a b cu cs
49 Multiplication of signed and unsigned LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.numeric_std.all ; numbers entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); cu : out STD_LOGIC_VECTOR(5 downto ); cs : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin -- signed multiplication cs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b)); -- unsigned multiplication cu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b)); end dataflow; 49
50 Multiplication of signed and unsigned LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.numeric_std.all ; numbers entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); cu : out STD_LOGIC_VECTOR(5 downto ); cs : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin -- signed multiplication cs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b)); -- unsigned multiplication cu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b)); end dataflow; 5
51 Comparators ECE 448 FPGA and ASIC Design with VHDL 5
52 4-bit Number Comparator 4 4 A B A > B AgtB 52
53 4-bit Unsigned Number Comparator 4 4 A B A > B AgtB U AgtB <= '' WHEN A > B ELSE '' ; 53
54 VHDL code for a 4-bit Unsigned Number Comparator entity LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AgtB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AgtB <= '' WHEN A > B ELSE '' ; END dataflow ; 54
55 VHDL code for a 4-bit Signed Number Comparator entity LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_signed.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AgtB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AgtB <= '' WHEN A > B ELSE '' ; END dataflow ; 55
56 4-bit Unsigned Number Comparator 4 4 A B AeqB AgtB AltB U 56
57 VHDL code for a 4-bit Unsigned Number Comparator LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AeqB <= '' WHEN A = B ELSE '' ; AgtB <= '' WHEN A > B ELSE '' ; AltB <= '' WHEN A < B ELSE '' ; END dataflow ; 57
58 VHDL code for a 4-bit Signed Number Comparator LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_signed.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AeqB <= '' WHEN A = B ELSE '' ; AgtB <= '' WHEN A > B ELSE '' ; AltB <= '' WHEN A < B ELSE '' ; END dataflow ; 58
59 Arithmetic operations Synthesizable arithmetic operations: Addition, + Subtraction, - Comparisons, >, >=, <, <= Multiplication, * Division by a power of 2, /2**6 (equivalent to right shift) 59
60 Arithmetic operations The result of synthesis of an arithmetic operation is a - combinational circuit - without pipelining. The exact internal architecture used (and thus delay and area of the circuit) may depend on the timing constraints specified during synthesis (e.g., the requested maximum clock frequency). 6
61 Integer Types Operations on signals of the integer types: INTEGER, NATURAL, and their sybtypes, such as TYPE day_of_month IS RANGE TO 3; are synthesizable in the range -(2 3 -) for INTEGERs and their subtypes for NATURALs and their subtypes 6
62 Integer Types Operations on signals (variables) of the integer types: INTEGER, NATURAL, are less flexible and more difficult to control than operations on signals (variables) of the type STD_LOGIC_VECTOR UNSIGNED SIGNED, and thus are recommened to be avoided by beginners. 62
63 ROM ECE 448 FPGA and ASIC Design with VHDL 63
64 ROM 8x6 example () Addr 3 8x6 ROM Dout 6 C 64
65 ROM 8x6 example (2) LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.numeric_std.all; ENTITY rom IS PORT ( ); Addr : IN STD_LOGIC_VECTOR(2 DOWNTO ); Dout : OUT STD_LOGIC_VECTOR(5 DOWNTO ) END rom; 65
66 ROM 8x6 example (3) ARCHITECTURE dataflow OF rom IS SIGNAL temp: INTEGER RANGE TO 7; TYPE vector_array IS ARRAY ( to 7) OF STD_LOGIC_VECTOR(5 DOWNTO ); CONSTANT memory : vector_array := ( X"8A", X"D459", X"A87", X"7853", X"65D", X"642F", X"F742", X"F548"); BEGIN temp <= to_integer(unsigned(addr)); Dout <= memory(temp); END dataflow; 66
67 ROM 8x6 example (4) ARCHITECTURE dataflow OF rom IS TYPE vector_array IS ARRAY ( to 7) OF STD_LOGIC_VECTOR(5 DOWNTO ); CONSTANT memory : vector_array := ( X"8A", X"D459", X"A87", X"7853", X"65D", X"642F", X"F742", X"F548"); BEGIN Dout <= memory(to_integer(unsigned(addr))); END dataflow; 67
68 Buffers ECE 448 FPGA and ASIC Design with VHDL 68
69 Tri-state Buffer e x f e = (a) A tri-state buffer x f e x f x e = (b) Equivalent circuit f (c) Truth table 69
70 Tri-state Buffer e x f e = (a) A tri-state buffer x f e x f Z Z x e = (b) Equivalent circuit f (c) Truth table 7
71 Four types of Tri-state Buffers e e x f x f f <= x WHEN (e(a) = '') ELSE 'Z'; f <= not x WHEN (b) (e = '') ELSE 'Z'; e e x f x f f <= x WHEN (e(c) = '') ELSE 'Z'; f <= not x WHEN (d) (e = '') ELSE 'Z'; 7
72 Tri-state Buffer entity () LIBRARY ieee; USE ieee.std_logic_64.all; ENTITY tri_state IS PORT ( e: IN STD_LOGIC; x: IN STD_LOGIC; f: OUT STD_LOGIC ); END tri_state; 72
73 Tri-state Buffer entity (2) ARCHITECTURE dataflow OF tri_state IS BEGIN f <= x WHEN (e = ) ELSE Z ; END dataflow; 73
74 MLU Example 74
75 MLU Block Diagram A A MUX_ MUX_4_ NEG_A MUX_ MUX_2 IN IN IN2 OUTPUT IN3 SEL SEL Y Y NEG_Y B B L L NEG_B MUX_3 75
76 MLU: Entity Declaration LIBRARY ieee; USE ieee.std_logic_64.all; ENTITY mlu IS PORT( NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L : IN STD_LOGIC; L : IN STD_LOGIC; ); END mlu; Y : OUT STD_LOGIC 76
77 MLU: Architecture Declarative Section ARCHITECTURE mlu_dataflow OF mlu IS SIGNAL A : STD_LOGIC; SIGNAL B : STD_LOGIC; SIGNAL Y : STD_LOGIC; SIGNAL MUX_ : STD_LOGIC; SIGNAL MUX_ : STD_LOGIC; SIGNAL MUX_2 : STD_LOGIC; SIGNAL MUX_3 : STD_LOGIC; SIGNAL L: STD_LOGIC_VECTOR( DOWNTO ); 77
78 MLU - Architecture Body BEGIN A<= NOT A WHEN (NEG_A='') ELSE A; B<= NOT B WHEN (NEG_B='') ELSE B; Y <= NOT Y WHEN (NEG_Y='') ELSE Y; MUX_ <= A AND B; MUX_ <= A OR B; MUX_2 <= A XOR B; MUX_3 <= A XNOR B; L <= L & L; with (L) select Y <= MUX_ WHEN "", MUX_ WHEN "", MUX_2 WHEN "", MUX_3 WHEN OTHERS; END mlu_dataflow; 78
79 Combinational Logic Synthesis for Beginners ECE 448 FPGA and ASIC Design with VHDL 79
80 Simple rules for beginners For combinational logic, use only concurrent statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) 8
81 Simple rules for beginners For circuits composed of - simple logic operations (logic gates) - simple arithmetic operations (addition, subtraction, multiplication) - shifts/rotations by a constant use concurrent signal assignment ( ) 8
82 Simple rules for beginners For circuits composed of - multiplexers - decoders, encoders - tri-state buffers use conditional concurrent signal assignment (when-else) (ending with ELSE) selected concurrent signal assignment (with-select-when) (ending with WHEN OTHERS;) 82
83 Example: VHDL code for a 4-to- MUX LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY mux4to IS PORT ( w, w, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR( DOWNTO ) ; f : OUT STD_LOGIC ) ; END mux4to ; ARCHITECTURE dataflow OF mux4to IS BEGIN WITH s SELECT f <= w WHEN "", w WHEN "", w2 WHEN "", w3 WHEN OTHERS ; END dataflow ; 83
84 when-else vs. with-select-when () "when-else" should be used when: ) there is only one condition (and thus, only one else), as in the 2-to- MUX 2) conditions are independent of each other (e.g., they test values of different signals) 3) conditions reflect priority (as in priority encoder); one with the highest priority need to be tested first. 84
85 when-else vs. with-select-when (2) "with-select-when" should be used when there is ) more than one condition 2) conditions are closely related to each other (e.g., represent different ranges of values of the same signal) 3) all conditions have the same priority (as in the 4-to- MUX). 85
86 Left vs. right side of the assignment Left side <= <= when-else with-select <= Right side Internal signals (defined in a given architecture) Ports of the mode - out - inout Expressions including: Internal signals (defined in a given architecture) Ports of the mode - in - inout 86
ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
Lecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1
Lecture 1: VHDL Quick Start Digital Systems Design Fall 10, Dec 17 Lecture 1 1 Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student s Guide to VHDL or The
ECE 545 Lecture 5. Data Flow Modeling in VHDL. George Mason University
ECE 545 Lecture 5 Data Flow Modeling in VHDL George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 4, Concurrent Signal Assignment Statements of VHDL 2 Types of VHDL Description
Chapter 6 Combinational-Circuit Building Blocks
Chapter 6 Combinational-Circuit Building Blocks Commonly used combinational building blocks in design of large circuits: Multiplexers Decoders Encoders Comparators Arithmetic circuits Multiplexers A multiplexer
ELE432. ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY Designing with VHDL
ELE432 ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY Designing with VHDL Organization of the Week Quartus II and simple I/O Combinational Sequential References Required P. Chu, FPGA Prototyping by VHDL
ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University
ECE 545 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 5.1, VHDL Process Chapter 8, Sequential
CprE 583 Reconfigurable Computing
Recap Moore FSM Example CprE / ComS 583 Reconfigurable Computing Moore FSM that recognizes sequence 10 0 1 0 1 S0 / 0 S1 / 0 1 S2 / 1 Prof. Joseph Zambreno Department of Electrical and Computer Engineering
Digital Systems Design
Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in
ECE 545 Lecture 12. FPGA Resources. George Mason University
ECE 545 Lecture 2 FPGA Resources George Mason University Recommended reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 2 What is an FPGA? Configurable Logic Blocks
ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. Behavioral Design Style: Registers & Counters.
ECE 55 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks Required reading P. Chu, RTL Hardware esign using VHL Chapter 5.1, VHL Process Chapter 8, Sequential Circuit esign: Principle
ECE 545 Lecture 7. VHDL Description of Basic Combinational & Sequential Circuit Building Blocks. Required reading. Fixed Shifters & Rotators
EE 55 Lecture 7 VHL escription o Basic ombinational & Sequential ircuit Building Blocks Required reading P. hu, RTL Hardare esign using VHL hapter 7, ombinational ircuit esign: Practice hapter 5., VHL
Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
ECE 545 Lecture 4. Simple Testbenches. George Mason University
ECE 545 Lecture 4 Simple Testbenches George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 2.2.4, Testbenches 2 Testbenches ECE 448 FPGA and ASIC Design with VHDL 3 Testbench
Lecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
ELCT 501: Digital System Design
ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)
Lecture 4. VHDL Fundamentals. George Mason University
Lecture 4 VHDL Fundamentals George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL 2 Design Entity ECE 448 FPGA and ASIC Design with
ECE 448 Lecture 4. Sequential-Circuit Building Blocks. Mixing Description Styles
ECE 448 Lecture 4 Sequential-Circuit Building Blocks Mixing Description Styles George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 4, Regular Sequential Circuit Recommended
EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 6 Combinational and sequential circuits
EE 459/5 HL Based igital esign with Programmable Logic Lecture 6 ombinational and sequential circuits Read before class: hapter 2 from textbook Overview ombinational circuits Multiplexer, decoders, encoders,
ECE 545 Lecture 12. Datapath vs. Controller. Structure of a Typical Digital System Data Inputs. Required reading. Design of Controllers
ECE 545 Lecture 12 Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts Required reading P. Chu, using VHDL Chapter 1, Finite State Machine: Principle & Practice Chapter
IE1204 Digital Design L7: Combinational circuits, Introduction to VHDL
IE24 Digital Design L7: Combinational circuits, Introduction to VHDL Elena Dubrova KTH / ICT / ES dubrova@kth.se This lecture BV 38-339, 6-65, 28-29,34-365 IE24 Digital Design, HT 24 2 The multiplexer
Contents. Appendix D VHDL Summary Page 1 of 23
Appendix D VHDL Summary Page 1 of 23 Contents Appendix D VHDL Summary...2 D.1 Basic Language Elements...2 D.1.1 Comments...2 D.1.2 Identifiers...2 D.1.3 Data Objects...2 D.1.4 Data Types...2 D.1.5 Data
VHDL for Complex Designs
ELEC 379 : DESIGN OF DIGITAL AND MICROCOMPUTER SYSTEMS 1998/99 WINTER SESSION, TERM 2 VHDL for Complex Designs This lecture covers VHDL features that are useful when designing complex logic circuits. After
Lecture 38 VHDL Description: Addition of Two [5 5] Matrices
![Lecture 38 VHDL Description: Addition of Two [5 5] Matrices](/thumbs/83/88753861.jpg "Lecture 38 VHDL Description: Addition of Two [5 5] Matrices")
Lecture 38 VHDL Description: Addition of Two [5 5] Matrices -- First, write a package to declare a two-dimensional --array with five elements library IEEE; use IEEE.STD_LOGIC_1164.all; package twodm_array
Writing VHDL for RTL Synthesis
Writing VHDL for RTL Synthesis Stephen A. Edwards, Columbia University December 21, 2009 The name VHDL is representative of the language itself: it is a two-level acronym that stands for VHSIC Hardware
Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University
Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.
310/ ICTP-INFN Advanced Tranining Course on FPGA and VHDL for Hardware Simulation and Synthesis 27 November - 22 December 2006
310/1780-10 ICTP-INFN Advanced Tranining Course on FPGA and VHDL for Hardware Simulation and Synthesis 27 November - 22 December 2006 VHDL & FPGA - Session 2 Nizar ABDALLH ACTEL Corp. 2061 Stierlin Court
ECE 545 Lecture 9. Modeling of Circuits with a Regular Structure. Aliases, Attributes, Packages. George Mason University
ECE 545 Lecture 9 Modeling of Circuits with a Regular Structure Aliases, Attributes, Packages George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapters 14.5 For Generate
Hardware Description Language VHDL (1) Introduction
Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 2
DIGITAL LOGIC WITH VHDL (Fall 23) Unit 2 Use of std_logic_vector. CONCURRENT DESCRIPTION with-select, when-else statements Examples: multiplexor, decoder. std_logic_vector In the example, we use the std_logic_vector
ECE 545 Lecture 7. Modeling of Circuits with a Regular Structure. Aliases, Attributes, Packages. Mixing Design Styles. George Mason University
ECE 545 Lecture 7 Modeling of Circuits with a Regular Structure Aliases, Attributes, Packages Mixing Design Styles George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapters
Advanced Training Course on FPGA Design and VHDL for Hardware Simulation and Synthesis. 26 October - 20 November, 2009
2065-15 Advanced Training Course on FPGA Design and VHDL for Hardware Simulation and Synthesis 26 October - 20 November, 2009 FPGA Architectures & VHDL Introduction to Synthesis Nizar Abdallah ACTEL Corp.2061
Control and Datapath 8
Control and Datapath 8 Engineering attempts to develop design methods that break a problem up into separate steps to simplify the design and increase the likelihood of a correct solution. Digital system
ECE 545: Lecture 11. Programmable Logic Memories
ECE 545: Lecture 11 Programmable Logic Memories Recommended reading Vivado Design Suite User Guide: Synthesis Chapter 4 RAM HDL Coding Techniques Initializing RAM Contents 7 Series FPGAs Memory Resources:
ECE 545: Lecture 11. Programmable Logic Memories. Recommended reading. Memory Types. Memory Types. Memory Types specific to Xilinx FPGAs
ECE 545: Lecture 11 Programmable Logic Memories Recommended reading Vivado Design Suite User Guide: Synthesis Chapter 4 RAM HDL Coding Techniques Initializing RAM Contents 7 Series FPGAs Resources: User
Introduction to VHDL. Main language concepts
Introduction to VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language Current standard is IEEE 1076-1993 (VHDL-93). Some tools still only support VHDL-87. Tools used in the lab
Chapter 2 Basic Logic Circuits and VHDL Description
Chapter 2 Basic Logic Circuits and VHDL Description We cannot solve our problems with the same thinking we used when we created them. ----- Albert Einstein Like a C or C++ programmer don t apply the logic.
Introduction to VHDL #3
ECE 322 Digital Design with VHDL Introduction to VHDL #3 Lecture 7 & 8 VHDL Modeling Styles VHDL Modeling Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral (sequential)
Lattice VHDL Training
Lattice Part I February 2000 1 VHDL Basic Modeling Structure February 2000 2 VHDL Design Description VHDL language describes a digital system as a set of modular blocks. Each modular block is described
Concurrent Signal Assignment Statements (CSAs)
Concurrent Signal Assignment Statements (CSAs) Digital systems operate with concurrent signals Signals are assigned values at a specific point in time. VHDL uses signal assignment statements Specify value
ACS College of Engineering. Department of Biomedical Engineering. Logic Design Lab pre lab questions ( ) Cycle-1
ACS College of Engineering Department of Biomedical Engineering Logic Design Lab pre lab questions (2015-2016) Cycle-1 1. What is a combinational circuit? 2. What are the various methods of simplifying
Lecture 4. VHDL Fundamentals. Required reading. Example: NAND Gate. Design Entity. Example VHDL Code. Design Entity
Required reading Lecture 4 VHDL Fundamentals P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL George Mason University 2 Example: NAND Gate Design Entity a b z a b z 0
Basic Language Concepts
Basic Language Concepts Sudhakar Yalamanchili, Georgia Institute of Technology ECE 4170 (1) Describing Design Entities a sum b carry Primary programming abstraction is a design entity Register, logic block,
CprE 583 Reconfigurable Computing
Recap 4:1 Multiplexer CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #18 VHDL for Synthesis I LIBRARY ieee
Very High Speed Integrated Circuit Har dware Description Language
Very High Speed Integrated Circuit Har dware Description Language Industry standard language to describe hardware Originated from work in 70 s & 80 s by the U.S. Departm ent of Defence Root : ADA Language
Review of Digital Design with VHDL
Review of Digital Design with VHDL Digital World Digital world is a world of 0 and 1 Each binary digit is called a bit Eight consecutive bits are called a byte Hexadecimal (base 16) representation for
Introduction to VHDL #1
ECE 3220 Digital Design with VHDL Introduction to VHDL #1 Lecture 3 Introduction to VHDL The two Hardware Description Languages that are most often used in industry are: n VHDL n Verilog you will learn
ECE 699: Lecture 9. Programmable Logic Memories
ECE 699: Lecture 9 Programmable Logic Memories Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques Sections: RAM HDL Coding Techniques ROM
Logic and Computer Design Fundamentals VHDL. Part 1 Chapter 4 Basics and Constructs
Logic and Computer Design Fundamentals VHDL Part Chapter 4 Basics and Constructs Charles Kime & Thomas Kaminski 24 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Overview
Digital System Construction
Digital System Construction FYSIKUM Lecture 4: More VHDL, memory, PRNG Arithmetic Memories Pipelines and buffers Pseudorandom numbers IP core generation in Vivado Introduction to Lab 3 Digital Systemkonstruktion
Lecture 3: Modeling in VHDL. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware
CS211 Digital Systems/Lab. Introduction to VHDL. Hyotaek Shim, Computer Architecture Laboratory
CS211 Digital Systems/Lab Introduction to VHDL Hyotaek Shim, Computer Architecture Laboratory Programmable Logic Device (PLD) 2/32 An electronic component used to build reconfigurable digital circuits
Multi-valued Logic. Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized
Multi-valued Logic Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized X, unknown 0, logic 0 1, logic 1 Z, high impedance W, unknown L, logic 0 weak H, logic 1 weak - ); don t care Standard
EEL 4712 Digital Design Test 1 Spring Semester 2008
IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. Also, as always, the best answer gets the most points. COVER SHEET: Problem:
Introduction to VHDL
Introduction to VHDL Agenda Introduce VHDL Basic VHDL constructs Implementing circuit functions Logic, Muxes Clocked Circuits Counters, Shifters State Machines FPGA design and implementation issues FPGA
VHDL simulation and synthesis
VHDL simulation and synthesis How we treat VHDL in this course You will not become an expert in VHDL after taking this course The goal is that you should learn how VHDL can be used for simulation and synthesis
The VHDL Hardware Description Language
The VHDL Hardware Description Language p. 1/? The VHDL Hardware Description Language CSEE W4840 Prof. Stephen A. Edwards Columbia University The VHDL Hardware Description Language p. 2/? Why HDLs? 1970s:
ECE U530 Digital Hardware Synthesis. Course Accounts and Tools
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu Sept 13, 2006 Lecture 3: Basic VHDL constructs Signals, Variables, Constants VHDL Simulator and Test benches Types Reading: Ashenden
VHDL. Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit
VHDL VHDL Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit VHDL Alternative (Student Generated) Definition Very Hard Digital Logic language VHDL Design
CSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\
![CSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\](/thumbs/74/70459415.jpg "CSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\")
CSCI 250 - Lab 3 VHDL Syntax Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\ Objectives 1. Learn VHDL Valid Names 2. Learn the presentation of Assignment and Comments 3. Learn Modes, Types, Array,
Using Library Modules in VHDL Designs
Using Library Modules in VHDL Designs This tutorial explains how Altera s library modules can be included in VHDL-based designs, which are implemented by using the Quartus R II software. Contents: Example
VHDL: Modeling RAM and Register Files. Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2
VHDL: Modeling RAM and Register Files Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2 Memory Synthesis Approaches: Random logic using flip-flops or latches Register files in datapaths RAM standard components
!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"
!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"!!"#$%&'#()#*+"+#,-."/0110#230#4."50",+"+#)6# 6+-+#(.6+-0#)4475.8)60#0/#.65-0#230#9+**+"+# 2.48).-0#(.6+-0#! 2+"*5."5*:#,."/0110#;)**0! *),".6*:#-.99-0*0"5."+#2+660,.40"5)#;)*)2)#
Using Library Modules in VHDL Designs
Using Library Modules in VHDL Designs This tutorial explains how Altera s library modules can be included in VHDL-based designs, which are implemented by using the Quartus R II software. Contents: Example
CHAPTER NINE - MSI Logic Circuits
CHAPTER NINE - MSI Logic Circuits 9. (a) All of the outputs are HIGH. (b) O =, O- O7 = (c) O - O6 =, O7 =. (d) Same as (a). 9.2 Inputs = 6: Outputs = 64 9.3 (a) [ O6] -> A2=, A=, A=, E3=, E2 =, E= (b)
INTRODUCTION TO VHDL. K. Siozios
INTRODUCTION TO VHDL K. Siozios Section of Electronics and Electronic Computers Department of Physics Aristotle University of Thessaloniki (AUTH), Greece Reconfigurable Architectures Today Moore s Law
Review. LIBRARY list of library names; USE library.package.object; ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type;
LIBRARY list of library names; USE library.package.object; Review ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type; signal_name(s) : mode signal_type); END ENTITY entity_name;
CMPT 250: Computer Architecture. Using LogicWorks 5. Tutorial Part 1. Somsubhra Sharangi
CMPT 250: Computer Architecture Using LogicWorks 5 Tutorial Part 1 Somsubhra Sharangi What is VHDL? A high level language to describe digital circuit Different that a programming language ( such as Java)
EEL 4783: Hardware/Software Co-design with FPGAs
EEL 4783: Hardware/Software Co-design with FPGAs Lecture 9: Short Introduction to VHDL* Prof. Mingjie Lin * Beased on notes of Turfts lecture 1 What does HDL stand for? HDL is short for Hardware Description
VHDL 2 Combinational Logic Circuits. Reference: Roth/John Text: Chapter 2
VHDL 2 Combinational Logic Circuits Reference: Roth/John Text: Chapter 2 Combinational logic -- Behavior can be specified as concurrent signal assignments -- These model concurrent operation of hardware
COE 405 Design Methodology Based on VHDL
COE 405 Design Methodology Based on VHDL Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Elements of VHDL Top-Down Design Top-Down Design with
VHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning
VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning Design Flow 418_02 2 VHDL Modules 418_02 3 VHDL Libraries library IEEE; use IEEE.std_logic_1164.all; std_logic Single-bit
Design a 4 bit-adder. Then design a 4-7 decoder to show the outputs. Output Sum(4 bits) Adder. Output carry(1 bit)
Csc 343 Lab 2 Sep 28. 07 Objective: Design a 4 bit-adder. Then design a 4-7 decoder to show the outputs. Structure: Input A (4 bits) Input B (4 bit) Adder Output Sum(4 bits) Output carry(1 bit) input cin
EEL 4712 Digital Design Test 1 Spring Semester 2007
IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. COVER SHEET: Problem: Points: 1 (15 pts) 2 (20 pts) Total 3 (15 pts) 4 (18 pts)
VHDL for FPGA Design. by : Mohamed Samy
VHDL for FPGA Design by : Mohamed Samy VHDL Vhdl is Case insensitive myvar = myvar = MYVAR IF = if = if Comments start with -- Comments can exist anywhere in the line Semi colon indicates the end of statements
CPE 626 Advanced VLSI Design Lecture 6: VHDL Synthesis. Register File: An Example. Register File: An Example (cont d) Aleksandar Milenkovic
CPE 626 Lecture 6: VHDL Synthesis Aleksandar Milenkovic http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04f/ milenka@ece.uah.edu Assistant Professor Electrical and Computer Engineering
Lecture 3 Introduction to VHDL
CPE 487: Digital System Design Spring 2018 Lecture 3 Introduction to VHDL Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 Managing Design
VHDL in 1h. Martin Schöberl
VHDL in 1h Martin Schöberl VHDL /= C, Java, Think in hardware All constructs run concurrent Different from software programming Forget the simulation explanation VHDL is complex We use only a small subset
Department of Electronics & Communication Engineering Lab Manual E-CAD Lab
Department of Electronics & Communication Engineering Lab Manual E-CAD Lab Prasad V. Potluri Siddhartha Institute of Technology (Sponsored by: Siddhartha Academy of General & Technical Education) Affiliated
VHDL: RTL Synthesis Basics. 1 of 59
VHDL: RTL Synthesis Basics 1 of 59 Goals To learn the basics of RTL synthesis. To be able to synthesize a digital system, given its VHDL model. To be able to relate VHDL code to its synthesized output.
INTRODUCTION TO VHDL ADVANCED COMPUTER ARCHITECTURES. Slides by: Pedro Tomás. Additional reading: - ARQUITECTURAS AVANÇADAS DE COMPUTADORES (AAC)
INTRODUCTION TO VHDL Slides by: Pedro Tomás Additional reading: - ADVANCED COMPUTER ARCHITECTURES ARQUITECTURAS AVANÇADAS DE COMPUTADORES (AAC) Outline 2 Hardware Description Languages (HDL) VHDL Very
VHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY. Design descriptions & design constructions examples are taken from foundation series examples
1 VHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY Design descriptions & design constructions examples are taken from foundation series examples 2 What we have done in Lab 1 entity AND_Gate is port ( a : in
FPGA BASED SYSTEM DESIGN. Dr. Tayab Din Memon Lecture 9 & 10 : Combinational and Sequential Logic
FPGA BASED SYSTEM DESIGN Dr. Tayab Din Memon tayabuddin.memon@faculty.muet.edu.pk Lecture 9 & 10 : Combinational and Sequential Logic Combinational vs Sequential Logic Combinational logic output depends
Using Library Modules in VHDL Designs. 1 Introduction. For Quartus II 12.1
Using Library Modules in VHDL Designs For Quartus II 12.1 1 Introduction This tutorial explains how Altera s library modules can be included in VHDL-based designs, which are implemented by using the Quartus
Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses
Today Comments about assignment 3-43 Comments about assignment 3 ASICs and Programmable logic Others courses octor Per should show up in the end of the lecture Mealy machines can not be coded in a single
ECE 448 Lecture 5. FPGA Devices
E 448 Lecture 5 FPGA evices E 448 FPGA and ASIC esign with VHL George Mason University Required reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional etails 2 What is an FPGA?
IT T35 Digital system desigm y - ii /s - iii
UNIT - V Introduction to Verilog Hardware Description Language Introduction HDL for combinational circuits Sequential circuits Registers and counters HDL description for binary multiplier. 5.1 INTRODUCTION
VHDL Structural Modeling II
VHDL Structural Modeling II ECE-331, Digital Design Prof. Hintz Electrical and Computer Engineering 5/7/2001 331_13 1 Ports and Their Usage Port Modes in reads a signal out writes a signal inout reads
Microcomputers. Outline. Number Systems and Digital Logic Review
Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded
[VARIABLE declaration] BEGIN. sequential statements
![[VARIABLE declaration] BEGIN. sequential statements](/thumbs/89/98890993.jpg "[VARIABLE declaration] BEGIN. sequential statements")
PROCESS statement (contains sequential statements) Simple signal assignment statement
Design units can NOT be split across different files
Skeleton of a Basic VHDL Program This slide set covers the components to a basic VHDL program, including lexical elements, program format, data types and operators A VHDL program consists of a collection
VHDL Examples Mohamed Zaky
VHDL Examples By Mohamed Zaky (mz_rasmy@yahoo.co.uk) 1 Half Adder The Half Adder simply adds 2 input bits, to produce a sum & carry output. Here we want to add A + B to produce Sum (S) and carry (C). A
C-Based Hardware Design
LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples
COVER SHEET: Total: Regrade Info: 5 (5 points) 2 (8 points) 6 (10 points) 7b (13 points) 7c (13 points) 7d (13 points)
EEL 4712 Midterm 2 Spring 2011 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read
Introduction to VHDL #2
ECE 322 Digital Design with VHDL Introduction to VHDL #2 Lecture 4 Signal Assignment Statements Forms of signal assignment statements: Simple Concurrent Assignment Selected Assignment Conditional Assignment
Design Using Verilog
EGC220 Design Using Verilog Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Basic Verilog Lexical Convention Lexical convention are close to C++. Comment // to the of the line. /* to
JUNE, JULY 2013 Fundamentals of HDL (10EC45) PART A
JUNE, JULY 2013 Fundamentals of HDL (10EC45) Time: 3hrs Max Marks:100 Note: Answer FIVE full questions, selecting at least TWO questions from each part. PART A Q1.a. Describe VHDL scalar data types with
Control Unit: Binary Multiplier. Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN
Control Unit: Binary Multiplier Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN Example: Binary Multiplier Two versions Hardwired control Microprogrammed
Arithmetic Circuits. Nurul Hazlina Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit
Nurul Hazlina 1 1. Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit Nurul Hazlina 2 Introduction 1. Digital circuits are frequently used for arithmetic operations 2. Fundamental
5. 0 VHDL OPERATORS. The above classes are arranged in increasing priority when parentheses are not used.
Filename= ch5.doc 5. 0 VHDL OPERATORS There are seven groups of predefined VHDL operators: 1. Binary logical operators: and or nand nor xor xnor 2. Relational operators: = /= < >= 3. Shifts operators: