Hardware Synthesis. Midia Reshadi. CE Department Science and research branch of Islamic Azad University

Transcription

1 Hardware Synthesis MidiaReshadi CE Department Science and research branch of Islamic Azad University Midia Reshadi 1 Chapter 6 Testbenches for Combinational Designs Midia Reshadi 2 1

2 Simple testbench Midia Reshadi 3 Simple testbench Simple testbench for a half adder using projected waveforms library ieee; use ieee.std_logic_1164.all; entity testbench is -- testbench entity has no ports end testbench; Midia Reshadi 4 2

3 Simple testbench architecture waveform of testbench is -- Stimulus signals - to connect testbench to UUT input ports signal a_tb, b_tb : std_logic; -- Observed signals - to connect testbench to UUT output ports signal sum_tb, carry_out_tb : std_logic; begin -- Unit Under Test port map UUT : entity half_adder port map (a => a_tb, b => b_tb, sum => sum_tb, carry_out => carry_out_tb ); -- Signal assignment statements generating stimulus values a_tb <= '0', '1' after 40 ns; b_tb <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns; end waveform; Simple testbench for a half adder using projected waveforms Midia Reshadi 5 Simple testbench After Clause a_tb <= '0', '1' after 40 ns; b_tb <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns; Syntax for a signal assignment statement with multiple waveform elements signal_assignment_statement ::= target <= value_expression [after time_expression] Midia Reshadi 6 3

4 After Clause Simple testbench Timing waveform from simulation of half-adder testbench. a_tb <= '0', '1' after 40 ns; b_tb <= '0', '1' after 20 ns, '0' after 40 ns, '1' Midia Reshadi 7 such as Time Frequency Voltage current. Physical types Midia Reshadi 8 4

5 Physical types Primary and Secondary Units The primary unit of measure, listed immediately after keyword units Is the smallest unit represented by the physical type. Physical type declaration syntax type identifier is range simple_expression (to downto) simple_expression units identifier ; -- primary unit declaration { identifier = physical_literal ; } -- secondary_unit_declarations end units [ physical_type_simple_name ]] Midia Reshadi 9 Type Time Physical types type time is range implementation_defined units fs; -- femtosecond ps = 1000 fs;-- picosecond ns = 1000 ps;-- nanosecond us = 1000 ns;-- microsecond ms = 1000 us;-- millisecond sec = 1000 ms; -- second min = 60 sec; -- minute hr = 60 min; -- hour end units; Midia Reshadi 10 5

6 Physical types Subtype Delay_length Package STANDARD also defines a subtype of time named delay_length subtype delay_length is time range 0 fs to time'high; Arithmetic Operations on Physical Types Can be applied to physical types Highest value of type time addition, subtraction, identity, and negation s1 <= '0' after prop_delay * 2; s2 <= '1' after prop_delay / 4; Midia Reshadi 11 Single process testbench Testbench for a half adder using a process to apply stimulus and assertion statements to check outputs Library ieee; use ieee.std_logic_1164.all; entity testbench is end testbench; Midia Reshadi 12 6

7 Single process testbench architecture behavior of testbench is -- Declare local signals to assign values to and to observe signal a_tb, b_tb, sum_tb, carry_out_tb : std_logic; begin -- Create an instance of the circuit to be tested uut: entity half_adder port map(a => a_tb, b => b_tb, sum => sum_tb, carry_out => carry_out_tb); -- Define a process to apply input stimulus and verify outputs tb : process Midia Reshadi 13 Single process testbench constant period: time := 20 ns; begin -- Apply every possible input combination a_tb <= '0'; --apply input combination 00 and check outputs b_tb <= '0'; wait for period; assert ((sum_tb = '0') and (carry_out_tb = '0')) report "test failed for input combination 00" severity error; a_tb <= '0'; --apply input combination 01 and check outputs b_tb <= '1'; wait for period; assert ((sum_tb = '1') and (carry_out_tb = '0')) report "test failed for input combination 01" severity error; a_tb <= '1'; --apply input combination 10 and check outputs b_tb <= '0'; wait for period; Midia Reshadi 14 7

8 Single process testbench assert ((sum_tb = '1') and (carry_out_tb = '0')) report "test failed for input combination 10" severity error; a_tb <= '1'; --apply input combination 11 and check outputs b_tb <= '1'; wait for period; assert ((sum_tb = '0') and (carry_out_tb = '1')) report "test failed for input combination 11" severity error; wait; -- indefinitely suspend process end process; end; Midia Reshadi 15 Single process testbench Assertion Statements Use of assertion statements eliminate the need to visually inspect timing waveforms (sum_tb = '0') and (carry_out_tb = '0') "test failed for input combination 00" Midia Reshadi 16 8

9 Wait statements A wait statement suspendsand resumesexecution of the process containing the statement. wait on sensitivity_list; wait until boolean_expression; wait for time_expression; wait; Syntax for a wait statement. wait_statement ::= wait [sensitivity_clause] [condition_clause] [timeout_clause] ; Midia Reshadi 17 Wait statements Example, execution of the statement: wait until interrupt = '1'; For example: If a wait statement contains both a sensitivity clause and a condition clause, wait on ie until interrupt = '1'; Wait For Midia Reshadi 18 9

10 Wait statements Wait For suspending for a time-out interval equal to its associated time_expression wait for period; --period was a constant equal to 20 ns. Multiple Condition Wait wait on ie until interrupt = '1' for period; Wait (Forever) wait by itself causes a process to suspend forever Use: to stop the testbench sexecution Midia Reshadi 19 Assertion and report An assertion statement checks whether a specified condition (the assertion) is true. Syntax for an assertion statement assertion_statement ::= assert condition [ report expression ] [ severity expression ] ; Midia Reshadi 20 10

11 Assertion and report Assertion Violation If the condition in the assert statement evaluates false If the assertion statement has no report clause The simulator displays the default error message Assertion violation. Severity Levels indicates the degree which an assertion violation affects operation what actions the simulator must take predefined in package STANDARD as: Midia Reshadi 21 Severity Levels Assertion and report type severity_level is ( note, warning, error, failure); Midia Reshadi 22 11

12 Assertion and report Severity Levels Note is simply used to display informative messages during a simulation Warning is used to indicate an unusual situation where the simulation can continue but may produce unusual results Error (default level) is used to indicate a situation where corrective action should be taken. Failure is used to indicate a situation that should never arise. Midia Reshadi 23 Assertion and report Report Statement A report statement displays a message every time it is executed. Syntax for a report statement report_statement ::= report expression [severity expression] ; Midia Reshadi 24 12

13 Assertion and report Report Clause Message Text The special character constants CR (carriage return) and/or LF (line feed) report "test failed" & CR LF & "for input combination 01 severity error; will print the two lines: test failed for input combination 01 Midia Reshadi 25 Assertion and report Image Attribute T image(x) returns the string representation of the expression x of type T. report "test failed for a_tb = " & std_logic image(a_tb) & " and b_tb = " & std_logic image(b_tb); test failed for a_tb = '1' and b_tb = '0' Midia Reshadi 26 13

14 Records and table lookup A simple way to specify both stimulus and expected response values is to use a table of constants similar to the table lookup technique Records A record is a composite type that consists of named elements that may be of different types Midia Reshadi 27 Records Records and table lookup record_declaration ::= type identifier is record identifier_list : element_subtype_definition ; { identifier_list : element_subtype_definition ; } endrecord [ record_type_simple_name ] Test Vector Records type test_vector is record a : std_logic; b : std_logic; sum : std_logic; carry_out : std_logic; end record; Midia Reshadi 28 14

15 Records Example type test_vector_array is array natural range <>) of test_vector; The actual table of constants, declared using named association constant test_vectors : test_vector_array := ( -- a, b, sum, carry_out (a => '0', b => '0', sum => '0', carry_out =>'0'), (a => '0', b => '1', sum => '1', carry_out =>'0'), (a => '1', b => '0', sum => '1', carry_out =>'0'), (a => '1', b => '1', sum => '0', carry_out =>'1')); Midia Reshadi 29 Records using positional association constant test_vectors : test_vector_array := ( -- a, b, sum, carry_out ('0', '0', '0', '0'), ('0', '1', '1', '0'), ('1', '0', '1', '0'), ('1', '1', '0', '1')); Midia Reshadi 30 15

16 Records and table lookup Table lookup testbench for a half adder library ieee; use ieee.std_logic_1164.all; entity testbench is end testbench; Midia Reshadi 31 Records and table lookup architecture table of testbench is -- Stimulus signals signal a : std_logic; signal b : std_logic; -- Observed signals signal sum : std_logic; signal carry_out : std_logic; -- Declare record type type test_vector is record a : std_logic; b : std_logic; sum : std_logic; carry_out : std_logic; end record; Midia Reshadi 32 16

17 Records and table lookup type test_vector_array is array (natural range <>) of test_vector; constant test_vectors : test_vector_array := ( -- a, b, sum, carry_out ('0', '0', '0', '0'), ('0', '1', '1', '0'), ('1', '0', '1', '0'), ('1', '1', '0', '1')); Midia Reshadi 33 Records and table lookup begin UUT : entity half_adder port map (a => a, b => b, sum => sum, carry_out => carry_out ); verify : process begin for i in test_vectors'range loop a <= test_vectors(i).a; b <= test_vectors(i).b; wait for 20 ns; assert (( sum = test_vectors(i).sum ) and (carry_out = test_vectors(i).carry_out)) Midia Reshadi 34 17

18 Records and table lookup report "test vector " & integer'image(i) & " failed"& " for input a = " & std_logic'image(a) & " and b = " & std_logic'image(b) severity error; end loop; wait; end process; end table; test vector 3 failed for input a = '1' and b = '1' Midia Reshadi 35 Computing stimulus & results Half-adder testbench that computes expected results library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity testbench is end testbench; Midia Reshadi 36 18

19 Computing stimulus &Results architecture behavior of testbench is -- Declare signals to assign values to and to observe signal a_tb, b_tb, sum_tb, carry_out_tb : std_logic; begin -- Create an instance of the circuit to be tested uut: entity half_adder port map(a => a_tb, b => b_tb, sum => sum_tb, carry_out => carry_out_tb); -- Define a process to apply input stimulus and test outputs Midia Reshadi 37 Computing stimulus &Results tb : process constant period: time := 20 ns; constant n: integer := 2; begin -- Apply every possible input combination for i in 0 to 2**n - 1 loop (a_tb, b_tb) <= to_unsigned(i,n); wait for period; assert ((sum_tb = (a_tb xor b_tb)) and (carry_out_tb = (a_tb and b_tb)) ) report "test failed" severity error; end loop; wait; -- indefinitely suspend process end process; end; Midia Reshadi 38 19

20 VHDL shift operators Logical Shifts shift Arithmetic is opposite Shifts Shift operators b" " sll 3 = b" b" " sll -3 = b" If n is a negative integer -> the direction of the b" " sra 2 = b" a copy of the leftmost bit is shifted A shift left arithmetic shifts in a copy of the rightmost bit of the original operand. For example: b" " sla 2 = b" " Midia Reshadi 39 Rotates Shift operators The rorand rolrotate operations are similar to the srl and sll shift operations except the bit rotated out of one end of the vector is rotated into the other end. Midia Reshadi 40 20

21 Stimulus order based Testbench for ic74f539 with stimulus application order based on UUT functionality library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity ic74f539_tb is end ic74f539_tb; Midia Reshadi 41 Stimulus order based architecture tb_architecture of ic74f539_tb is -- Stimulus signals signal a : std_logic_vector(1 downto 0); signal p : std_logic; signal e_bar : std_logic; signal oe_bar : std_logic; -- Observed signals signal o : std_logic_vector(3 downto 0); -- stimulus application interval constant period : time := 20 ns; Midia Reshadi 42 21

22 Stimulus order based Midia Reshadi 43 Stimulus order based begin -- Unit Under Test port map UUT : entity ic74f539 port map (a => a, p => p, e_bar => e_bar, oe_bar => oe_bar, o => o); -- Stimulus and monitor process stim_mon: process variable o_exp : std_logic_vector(3 downto 0); begin -- verify output enable functionality oe_bar <= '1'; for i in 0 to 15 loop (p, e_bar, a(1), a(0)) <= to_unsigned(i, 4); wait for period; assert (o = "ZZZZ") report "output enable failed" severity error; end b; Midia Reshadi 44 22

23 Stimulus order based Midia Reshadi 45 Stimulus order based -- verify enable unasserted functionalify oe_bar <= '0'; e_bar <= '1'; for i in 0 to 7 loop (p, a(1), a(0)) <= to_unsigned(i, 3); wait for period; o_exp := p & p & p & p; assert (o = o_exp) report "enable unasserted failed" severity error; end loop; Midia Reshadi 46 23

24 Stimulus order based Midia Reshadi 47 Stimulus order based -- verify enable asserted decoder functionality e_bar <= '0'; for i in 0 to 7 loop (p, a(1), a(0)) <= to_unsigned(i, 3); wait for period; o_exp := (p & p & p & p) xor to_stdlogicvector("0001" rol to_integer(unsigned(a))); assert (o = o_exp) report "enable asserted failed" severity error; end loop; wait; end process; end tb_architecture; Midia Reshadi 48 24

25 Stimulus order based Converting a Bit_vector to a Std_logic_vector Midia Reshadi 49 Comparing to a behavioral Comparing to a behavioral intend model 3-to-8 decoder nonsynthesizable intent model library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity decoder_3to8_mod is port ( c, b, a : in std_logic; -- select inputs g1, g2a_bar, g2b_bar: in std_logic; -- enable inputs y_mod : out std_logic_vector(7 downto 0) ); end decoder_3to8_mod; Midia Reshadi 50 25

26 Comparing to a behavioral architecture rotate of decoder_3to8_mod is begin y_mod <= to_stdlogicvector (B"1111_1110" rol to_integer(unsigned'(c, b, a))) when unsigned (g1, g2a_bar, g2b_bar) = "100" else " "; end rotate; Midia Reshadi 51 Comparing to a behavioral A testbenchthat compares the outputs of two models library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity decoder_3to8_tb is end decoder_3to8_tb; Midia Reshadi 52 26

27 Comparing to a behavioral architecture tb_architecture of decoder_3to8_tb is -- Stimulus signals signal c : std_logic; signal b : std_logic; signal a : std_logic; signal g1 : std_logic; signal g2a_bar : std_logic; signal g2b_bar : std_logic; -- Observed signals signal y : std_logic_vector(7 downto 0); signal y_mod : std_logic_vector(7 downto 0); Midia Reshadi 53 Comparing to a behavioral begin -- Unit Under Test port map UUT : entity decoder_3to8 port map (c => c, b => b, a => a, g1 => g1, g2a_bar => g2a_bar, g2b_bar => g2b_bar, y => y ); -- Behavioral Model port map UMOD : entity decoder_3to8_mod port map (c => c, b => b, a => a, g1 => g1, g2a_bar => g2a_bar,g2b_bar => g2b_bar, y_mod => y_mod ); -- Stimulus and verification process tb: process constant period : time := 100 ns; Midia Reshadi 54 27

28 Comparing to a behavioral begin for i in 0 to 63 loop (c, b, a, g1, g2a_bar, g2b_bar) <= std_logic_vector(to_unsigned(i, 6)); wait for period; assert y = y_mod report "error for input vector " & integer'image(i) severity error; end loop; wait; end process; end tb_architecture; Midia Reshadi 55 Code Coverage Tool Code Coverage Determine what source code is executed during a simulation Hierarchy window of code coverage viewer Midia Reshadi 56 28

29 Code coverage view of source code for half adder 4 input by testbench (truth table) + simulation initialization Midia Reshadi 57 Code Coverage Code coverage view of half-adder testbench Midia Reshadi 58 29

30 Branch Coverage Code Coverage Branch coverage view of behavioral half adder Midia Reshadi 59 Post synthesis Hazards in Combinational Circuits A hazard is an output glitch caused by the gate-level structure of a circuit and the propagation delays of its individual gates. Static Hazard brief change (glitch) is caused by differences in propagation delays through different signal paths in the circuit. Dynamic Hazard A dynamic hazard occurs when a change in the input values to a combinational circuit causes an output to briefly change value multiple times when it should have changed value only once Midia Reshadi 60 30

31 Post synthesis Static and dynamic hazards: (a) static 0 hazard (b) static 1 hazard (c) dynamic 0 hazard (d) dynamic 1 hazard. Midia Reshadi 61 Timing verification Using Assertions to Verify Timing in Combinational Systems Process to verify logic and timing of half-adder timing model. tb : process constant tpd_spec : time := 11 ns; constant period: time := 20 ns; constant n: integer := 2; begin -- Apply every possible input combination for i in 0 to 2**n - 1 loop (a_tb,b_tb) <= to_unsigned(i,n); -- Verify output values at specified time wait for tpd_spec; Midia Reshadi 62 31

32 Timing verification assert ((sum_tb = (a_tb xor b_tb)) and (carry_out_tb = (a_tb and b_tb))) report "test failed for a_tb = " & std_logic'image(a_tb) & " and b_tb = " & std_logic'image(b_tb) severity error; -- Verify that outputs do not subsequently chnage Wait for period - tpd_spec; assert sum_tb'quiet(period - tpd_spec) and carry_out_tb'quiet(period - tpd_spec) report "propagation delay specification exceded" severity error; end loop; wait; end process; end; Midia Reshadi 63 Timing verification Process to verify logic and timing of halfadder timing model. Quiet is true when no transaction is occured Midia Reshadi 64 32

33 Timing Model the timing model automatically generated by the place-and-route tool. the timing model consists of two files a delaylessstructural VHDL netlist a non-vhdl text file that contains timing delay information Generics can be any type entity_declaration ::= entity identifier is [ generic ( generic_interface_list ) ; ] [ port ( port_interface_list ) ; ] end [ entity ] [ entity_simple_name ] ; Midia Reshadi 65 Timing Model Generics (Cont, ) Generics in a Timing Model Specifying delay times Trivial timing model for a half adder library ieee; use ieee.std_logic_1164.all; entity half_adder is generic ( tpd : time := 10 ns); port (a, b : in std_logic; sum, carry_out: out std_logic); end half_adder; Midia Reshadi 66 33

34 Timing Model architecture dataflow of half_adder is begin sum <= a xor b after tpd; carry_out <= a and b after tpd; end dataflow; Midia Reshadi 67 Netlist Block diagram of interconnection of SPARTAN II primitives to implement a half adder. Midia Reshadi 68 34

35 Netlist Partial VHDL netlist generated by a place-and-route tool library IEEE; use IEEE.STD_LOGIC_1164.ALL; library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity half_adder is port ( sum : out STD_LOGIC; a : in STD_LOGIC := 'X'; Midia Reshadi 69 Netlist b : in STD_LOGIC := 'X'; carry_out : out STD_LOGIC ); end half_adder; architecture Structure of half_adder is signal a_c_0 : STD_LOGIC; signal b_c_0 : STD_LOGIC; signal carry_out_outmux_0 : STD_LOGIC; signal sum_outmux_1 : STD_LOGIC; signal a_c : STD_LOGIC; signal b_c : STD_LOGIC; signal sum_c : STD_LOGIC; signal carry_out_c : STD_LOGIC; signal VCC : STD_LOGIC; Midia Reshadi 70 35

36 Netlist begin -- several component instances have been removed sum_0_x2 : X_LUT4 generic map(init => X"5A5A", LOC => "CLB_R4C1.S0" ) port map (ADR0 => b_c_0, ADR1 => VCC, ADR2 => a_c_0, ADR3 => VCC, O => sum_c); sum_outmux : X_BUF generic map(loc => "PAD85") port map (I => sum_c, O => sum_outmux_1 ); sum_obuf : X_OBUF generic map(loc => "PAD85") port map (I => sum_outmux_1, O => sum ); end Structure; Midia Reshadi 71 SDF Standard Delay Format (SDF) was originally developed by Cadence Design Systems A file format for conveying timing and delay information between EDA tools For simulation of designs written in the Verilog language SDF is now used to convey timing and delay information into both VHDL and Verilog simulations Midia Reshadi 72 36

37 SDF SDF contains constructs for the description of computed timing data for back annotation and the specification of timing constraints for forward annotation. An individual component in a technology library is called a cell. Midia Reshadi 73 SDF Partial SDF file for half-adder simulation (DELAYFILE (SDFVERSION "3.0") (DESIGN "half_adder") (DATE "Tue May 29 15:43: ") (VENDOR "Xilinx") (PROGRAM "Xilinx SDF Writer") (VERSION "I.24") (DIVIDER /) (VOLTAGE 2.375) (TEMPERATURE 85) (TIMESCALE 1 ps) ) Midia Reshadi 74 37

38 SDF (CELL(CELLTYPE "X_LUT4") (INSTANCE sum_0_x2) (DELAY (ABSOLUTE (PORT ADR0 (568)) (PORT ADR2 (1022)) (IOPATH ADR0 O (284)) (IOPATH ADR1 O (284)) (IOPATH ADR2 O (284)) (IOPATH ADR3 O (284)) ) (CELL(CELLTYPE "X_BUF") (INSTANCE carry_out_outmux) (DELAY Midia Reshadi 75 SDF (DELAY (ABSOLUTE (IOPATH I O (2603)) (CELL (CELLTYPE "X_OBUF") (INSTANCE sum_obuf) (DELAY (ABSOLUTE (PORT I (1042)) (IOPATH I O ( 3428)) Midia Reshadi 76 38

39 VITAL Simulation vahyt-l Waveforms from timing simulation of half adder implemented in a SPARTAN II FPGA. Midia Reshadi 77 Questions? Midia Reshadi 78 39