Hardware Synthesis. References
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1 Hardware Synthesis MidiaReshadi CE Department Science and research branch of Islamic Azad University 1 References 2 1
2 Chapter 1 Digital Design Using VHDL and PLDs 3 Some Definitions Hardware Description Languages (HDLs) VHDL and Verilog HDLs EDA Software Tools Programmable Logic Devices (PLDs) 4 2
3 VHDL/PLD Design Flow 5 Half-Adder Requirements and Specification A natural language requirements definition We need to be able to add two one-bit binary numbers 6 3
4 Design Description sum = a b + a b carry_out= a b 7 VHDL Editor Notepad++ Other definitions Keywords and comments 8 4
5 Other definitions Read from the text book: Verification Testbench UUT 9 Testbench library ieee; use ieee.std_logic_1164.all; entity testbenchis end testbench; architecture behavior of testbenchis -- Declare signals to assign values to and to observe signal a_tb, b_tb, sum_tb, carry_out_tb : std_logic; begin -- Create an instance of the circuit to be tested uut: entity half_adderport map(a => a_tb, b => b_tb, sum => sum_tb, carry_out => carry_out_tb); -- Define a process to apply input stimulus and test outputs tb: process constant period: time := 20 ns; begin -- Apply every possible input combination a_tb <= '0'; --apply input combination 00 and check outputs b_tb<= '0'; wait for period; 10 5
6 assert ((sum_tb= '0') and (carry_out_tb= '0')) report "test failed for input combination 00" severity error; a_tb <= '0'; --apply input combination 01 and check outputs b_tb <= '1'; wait for period; assert ((sum_tb= '1') and (carry_out_tb= '0')) report "test failed for input combination 01" severity error; a_tb <= '1'; --apply input combination 10 and check outputs b_tb<= '0'; wait for period; assert ((sum_tb= '1') and (carry_out_tb= '0')) report "test failed for input combination 10" severity error; a_tb <= '1'; --apply input combination 11 and check outputs b_tb<= '1'; wait for period; assert ((sum_tb = '0') and (carry_out_tb = '1')) report "test failed for input combination 11" severity error; wait; -- indefinitely suspend process end process; end; 11 Functional Simulation 12 6
7 13 FUNCTIONAL (BEHAVIORAL) SIMULAT ION Waveforms from the functional simulation Debugging Single step through source code statements Set breakpoints on source code statements Set breakpoints on signal or variable changes in value Monitor (watch) signal and variable values 14 7
8 ICs fixed-function IC ASIC programmable logic devices (PLDs) Simple PLDs (SPLDs) complex PLDs (CPLDs) Field programmable gate arrays (FPGAs) Logic Capacity (two-input NAND) SPLD 500 gates CPLD 60,000 FPGA 10,000 8,000,000 and now >8,000, A SPLD logic diagram Concepts: AND/OR Arrays Buffered Inputs Product Line Programmable Interconnects Sum Line Programmable Array Logic (PAL) Halfadder unprogrammedand programmed 16 8
9 Output Logic Macrocells (OLMCs) 17 Output Logic Macrocells (OLMCs) CombinationalMacrocell Output S0 and S1 Registered MacrocellOutput D flip flop 18 9
10 The 22V10 SPLD 19 The 22V10 SPLD 20 10
11 Logic Synthesis area (number of gates) number of gate level Synthesizer synthesize logic behaves identically to the simulated behavior of the design description. 21 post-synthesis simulation 22 11
12 Language synthesis Gate-Level Logic Optimization: algorithms Technology mapping RTL view of half-adder synthesized logic from synthesis 23 Gate-Level Logic Technology dependent view of half-adder synthesized logic from synthesis 24 12
13 Synthesizer Output VHDL netlist Technology dependent gate-level netlist Netlist a textual representation of the interconnection of logic elements. EDIF Netlist Format EDIF (Electronic Data Interchange Format) a standard format for transferring design information between EDA tools. 25 PLACE-AND-ROUTE AND TIMING SIMULATION Place-and-Route Operations A pace-and-route (or fitter) tool Pin Assignments User-Defined Attributes Place-and-Route Tool Outputs a chip report a configuration file a VHDL timing model 26 13
14 timing simulation portion 27 PLACE-AND-ROUTE AND TIMING SIMULATION Place-and-Route Tool Outputs a chip report a configuration file a VHDL timing model 28 14
15 A chip report 29 Timing (Post-Route) Simulation postroute, post-fit, or post-implementation simulations, 30 15
16 Design Flow Manager AldecActive-HDL Design Flow Manager. 31 PROGRAMMING AND VERIFYING A TARGET PLD JEDEC file (programming file or fuse map) The configuration file generated by the placeand-route tool Device Programmer connecting to a host computer In-System Programming Programming placing on a printed circuit board Concept: intellectual property (IP) 32 16
17 Questions? MidiaReshadi 33 17
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