Chapter 10. case studies in sequential logic design

Transcription

1 Chapter. case studies in sequential logic design This is the last chapter of this course. So far, we have designed several sequential systems. What is the general procedure? The most difficult part would be to draw the state diagram from the given problem. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz

2 Sequential logic examples Basic design approach: a 4-step design process Hardware description languages and finite state machines Implementation examples and case studies finite-string pattern recognizer complex counter traffic light controller door combination lock So we will focus on the first step of the design procedure with 4 examples, some of which are already partially introduced. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 2

3 General FSM design procedure () Determine inputs and outputs (2) Determine possible states of machine state minimization (3) Encode states and outputs into a binary code state assignment or state encoding output encoding possibly input encoding (if under our control) (4) Realize logic to implement functions for states and outputs combinational logic implementation and optimization choices in steps 2 and 3 can have large effect on resulting logic This is a somewhat more general design procedure. In step2, after identifying the states, we may be able to reduce the number of states. Step 3 has a big effect on the complexity of the overall system. If possible, we can decide how to encode input and output variables. In step 4, we can use random logic, shift registers/counters, or PLD like PAL X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 3

4 Finite string pattern recognizer (step ) Finite string pattern recognizer one input (X) and one output (Z) output is asserted whenever the input sequence has been observed, as long as the sequence has never been seen Step : understanding the problem statement sample input/output behavior: X: Z: X: Z: The first example is the finite string pattern recognizer. The output will be true when the recently read three bits are. And when (indicated by a pink dotted line) comes in to the system, the system will not assert the output. In this example, the bit string starts from the left. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 4

5 Finite string pattern recognizer (step 2) Step 2: draw state diagram for the strings that must be recognized, i.e., and a Moore implementation reset S [] S [] S4 [] S2 [] S3 [] S5 [] S6 [] or The need to illustrate inputs and outputs is to draw the state diagram more easily and correctly. Let s consider the key input patterns first for simplicity. There are two threads or flows to check and X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 5

6 Finite string pattern recognizer (step 2, cont d) Exit conditions from state S3: have recognized if next input is then have =... (state S6) if next input is then have = (state S2) Exit conditions from S: recognizes strings of form (no seen) loop back to S if input is Exit conditions from S4: recognizes strings of form (no seen) loop back to S4 if input is Let s consider S3 first. If S3 reads the next bit, then that happens to be the bit string that make the system move to the terminal state, S6. If S3 reads, then that is another bit pattern, it should wait for to come. reset... S [] S2 []... S []... S3... []... S4 [] S5 [] S6 [] or So, after we have seen, then the next bit is critical. If the following bit is, then the system will go to state S6, in which the input doesn t matter any longer. From S, input will make the system keep on checking the next input. Likewise S4 will sustain while X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 6 input iterates.

7 Finite string pattern recognizer (step 2, cont d) S2 and S5 still have incomplete transitions S2 = ; If next input is, then string could be prefix of ()() S4 handles just this case S5 = ; If next input is, then string could be prefix of ()() S2 handles just this case Reuse states as much as possible look for same meaning state minimization leads to smaller number of bits to represent states Once all states have a complete set of transitions we have a final state diagram X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 7 reset... S [] S2 []... S []... S3... []... S4 [] S5 [] S6 []... or Let s see S2. If S2 reads input, that means input will not happen now. Rather it should switch to the other thread to check whether will come or not. Similarly, S5 expects, but if it reads, it knows will not happen now. Instead, has been read, which may generate if the next bit is. So it will switch the flow by moving to S2

8 Finite string pattern recognizer (step 3) Verilog description including state assignment (or state encoding) module string (clk, X, rst, Q, Q, Q2, Z); input clk, X, rst; output Q, Q, Q2, Z; parameter S = [,,]; //reset state parameter S = [,,]; //strings ending in... parameter S2 = [,,]; //strings ending in... parameter S3 = [,,]; //strings ending in... parameter S4 = [,,]; //strings ending in... parameter S5 = [,,]; //strings ending in... parameter S6 = [,,]; //strings ending in... reg state[:2]; assign Q = state[]; assign Q = state[]; assign Q2 = state[2]; assign Z = (state == S3); clk) begin if (rst) state = S; else case (state) S: if (X) state = S4 else state = S; S: if (X) state = S2 else state = S; S2: if (X) state = S4 else state = S3; S3: if (X) state = S2 else state = S6; S4: if (X) state = S4 else state = S5; S5: if (X) state = S2 else state = S6; S6: state = S6; default: begin $display ( invalid state reached ); state = 3 bxxx; end endcase end endmodule After finishing the state diagram, we have two choices. The first option is to write a state transition table and construct the combinational logic part. The other option is to use the logic compiler by specifying the program in one of HDLs. In the above description, X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 8 sequential encoding is used for state assignment.

9 Finite string pattern recognizer Review of process understanding problem write down sample inputs and outputs to understand specification derive a state diagram write down sequences of states and transitions for sequences to be recognized minimize number of states add missing transitions; reuse states as much as possible state assignment or encoding encode states with unique patterns simulate realization verify I/O behavior of your state diagram to ensure it matches specification This is the overall procedure to design a sequential logic system. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 9

10 Complex counter A synchronous 3-bit counter has a mode control M when M =, the counter counts up in the binary sequence when M =, the counter advances through the Gray code sequence binary:,,,,,,, Gray:,,,,,,, Valid I/O behavior (partial) Mode Input M Current State Next State The 2 nd example is a complex counter. It has two modes. It will increment numbers by either binary encoding or Gray encoding. There will be total 6 cases, but only 7 cases are listed. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz

11 Complex counter (state diagram) Deriving state diagram one state for each output combination add appropriate arcs for the mode control reset S [] S [] S2 [] S3 [] S4 S5 S6 [] [] [] S7 [] If M is, the counter will move between states by the binary sequence. If M is, then the system will make transitions by Gray coding. You can see the system goes back and forth if M is. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz

12 Complex counter (state encoding) Verilog description including state encoding module string (clk, M, rst, Z, Z, Z2); input clk, X, rst; output Z, Z, Z2; parameter S = [,,]; parameter S = [,,]; parameter S2 = [,,]; parameter S3 = [,,]; parameter S4 = [,,]; parameter S5 = [,,]; parameter S6 = [,,]; parameter S7 = [,,]; reg state[:2]; assign Z = state[]; assign Z = state[]; assign Z2 = state[2]; clk) begin if rst state = S; else case (state) S: state = S; S: if (M) state = S3 else state = S2; S2: if (M) state = S6 else state = S3; S3: if (M) state = S2 else state = S4; S4: if (M) state = S else state = S5; S5: if (M) state = S4 else state = S6; S6: if (M) state = S7 else state = S7; S7: if (M) state = S5 else state = S; endcase end endmodule Here is the Verilog program to describe the complex counter. * little endian vs. big endian. A wire width or register width is specified by [msb : lsb] (most-significant-bit to least-significant-bit). The msb and lsb must be integers. Either little-endian convention (the lsb is the smallest bit number) or big-endian convention (the lsb is the largest bit number) X - Sequential will Logic be used. Case Studies Here big Copyright endian 24, is Gaetano used. Borriello and Randy H. Katz 2

13 Traffic light controller as two communicating FSMs Without separate timer HG would require 5 states HY would require 5 states FG would require 5 states TS' HY TS/ST HY HY2 FY would require 5 states HY and FY have simple transformation HY5 /ST HG and FG would require many more arcs C could change in any of 5 states By factoring out timer traffic light controller greatly reduce number of states counter only requires 5 or 5 states ST timer TS TL The next example is the traffic light controller. We didn t talk much about the timer expiration mechanism in chapter 9. Suppose TL and TS expire after 5 and 5 clock cycles, respectively. By splitting the timer-related function from the main FSM, we can achieve a much simpler design. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 3

14 Traffic light controller FSM Specification of inputs, outputs, and state elements module FSM(HR, HY, HG, FR, FY, FG, ST, TS, TL, C, reset, Clk); output HR; output HY; output HG; output FR; output FY; output FG; output ST; input TS; input TL; assign HR = state[6]; input C; assign HY = state[5]; input reset; assign HG = state[4]; input Clk; assign FR = state[3]; assign FY = state[2]; assign FG = state[]; reg [6:] state; reg ST; parameter highwaygreen = 6'b; parameter highwayyellow = 6'b; parameter farmroadgreen = 6'b; parameter farmroadyellow = 6'b; specify state bits and codes for each state as well as connections to outputs Among 7 outputs, six of them are going to the external light devices for highway and farmroad. Output ST actually goes to the timer module. As inter-fsm signals, TL and TS are coming from the timer module. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 4

15 Traffic light controller FSM (cont d) initial begin state = highwaygreen; ST = ; end Clk) begin if (reset) begin state = highwaygreen; ST = ; end else begin ST = ; case (state) highwaygreen: end endmodule case statement triggered by clock edge if (TL & C) begin state = highwayyellow; ST = ; end highwayyellow: if (TS) begin state = farmroadgreen; ST = ; end farmroadgreen: if (TL!C) begin state = farmroadyellow; ST = ; end farmroadyellow: if (TS) begin state = highwaygreen; ST = ; end endcase end Initially, ST is zero since probably there is little traffic on the farmroad. Thanks to the timer module, the overall behavior is very simplified. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 5

16 Timer for traffic light controller Another FSM module Timer(TS, TL, ST, Clk); output TS; output TL; input ST; input Clk; integer value; assign TS = (value >= 4); // 5 cycles after reset assign TL = (value >= 4); // 5 cycles after reset ST) value = ; // async reset Clk) value = value + ; endmodule This Verilog code specifies the behavior of the timer module. Actually, it increments the value variable at every clock. Depending on the current binary value of value, TS and/or TL will be set independently. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 6

17 Complete traffic light controller Tying it all together (FSM + timer) structural Verilog (same as a schematic drawing) module main(hr, HY, HG, FR, FY, FG, reset, C, Clk); output HR, HY, HG, FR, FY, FG; input reset, C, Clk; Timer part(ts, TL, ST, Clk); FSM part2(hr, HY, HG, FR, FY, FG, ST, TS, TL, C, reset, Clk); endmodule traffic light controller ST timer TS TL There are two external inputs: reset and C. On the right, there are six outputs for traffic lights in highway and farmroad directions. The clock signal is skipped. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 7

18 Communicating finite state machines One machine's output is another machine's input X FSM FSM 2 CLK Y FSM X A A B Y== A [] B [] Y== Y== X== X== C [] D [] X== X== X== FSM2 Y C D D machines advance in lock step initial inputs/outputs: X =, Y = Let s see how two FSMs are proceeding with synchronization. Suppose initially outputs are s (X=Y=). X is the output of FSM and Y is the output of FSM2. First, X= makes FSM2 move to state C and Y= makes FSM go to state A. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 8

19 Data-path and control Digital hardware systems = data-path + control datapath: registers, counters, combinational functional units (e.g., ALU), communication (e.g., busses) control: FSM generating sequences of control signals that instructs datapath what to do next control "puppeteer who pulls the strings" status info and inputs state control signal outputs data-path "puppet" To make it easy to design complicated systems, one of the popular ways is to divide-andconquer. In many electronic devices including computers, data-related functions are often split from the control part. The same dichotomy happens in humans. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 9

20 Digital combinational lock Door combination lock: punch in 3 values in sequence and the door opens; if there is an error the lock must be reset; once the door opens the lock must be reset inputs: sequence of input values, reset outputs: door open/close memory: must remember combination or always have it available open questions: how do you set the internal combination? stored in registers (how loaded?) hardwired via switches set by user In chapter, we looked at the door combination lock system. In the sketchy design, we split the data functions and control functions. We will detail all the modules from now on. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 2

21 Implementation in software integer combination_lock ( ) { integer v, v2, v3; integer error = ; static integer c[3] = 3, 4, 2; while (!new_value( )); v = read_value( ); if (v!= c[]) then error = ; while (!new_value( )); v2 = read_value( ); if (v2!= c[2]) then error = ; while (!new_value( )); v3 = read_value( ); if (v2!= c[3]) then error = ; if (error == ) then return(); else return (); } For compatibility with the textbook, assume that index starts with in the array. Here the store numbers are 3, 4, 2. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 2

22 Determining details of the specification How many bits per input value? How many values in sequence? How do we know a new input value is entered? What are the states and state transitions of the system? new value reset clock open/closed This is the whole system treated like a black box. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 22

23 Digital combination lock state diagram States: 5 states represent point in execution of machine each state has outputs Transitions: 6 from state to state, 5 self transitions, global changes of state occur when clock says its ok based on value of inputs Inputs: reset, new, results of comparisons Output: open/closed reset closed C!=value C2!=value C3!=value & new & new & new S S2 S3 OPEN C==value & new closed C2==value & new closed C3==value & new closed open ERR not new not new There are 5 states. One initial state and two terminal states. not new X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 23

24 Data-path and control structure Data-path storage registers for combination values multiplexer comparator Control finite-state machine controller control for data-path (which value to compare) value 4 C C2 C multiplexer 4 comparator mux control equal new controller reset clock open/closed On the left, there are data-related modules and wires. And control functions are located on the right. Some of the wires are 4 bits wide, and there are wires of other widths. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 24

25 State table for combination lock Finite-state machine refine state diagram to take internal structure into account state table ready for encoding next reset new equal state state mux open/closed S C closed S S C closed S ERR closed S S2 C2 closed... S3 OPEN open... Let s consider the controller part first. The states are normally handled only in the control modules. Some state transitions are omitted. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 25

26 Encodings for combination lock Encode state table state can be: S, S2, S3, OPEN, or ERR needs at least 3 bits to encode:,,,, and as many as 5:,,,, choose 4 bits:,,,, output mux can be: C, C2, or C3 needs 2 to 3 bits to encode choose 3 bits:,, output open/closed can be: open or closed needs or 2 bits to encode choose bit:, reset new equal state next state mux open/closed mux control equal open/closed mux is identical to last 3 bits of state open/closed is identical to first bit of state therefore, we do not even need to implement FFs to hold state, just use outputs X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 26 new controller There are many choices in encoding states, inputs, and outputs. We want to utilize many common bits between the state and the MUX control. reset clock

27 Data-path implementation for combination lock Multiplexer easy to implement as combinational logic when few inputs logic can easily get too big for most PLDs value_i Ci C2i C3i mux control C C2 C multiplexer 4 mux control value 4 comparator equal equal Now data parts are remaining. A MUX is simple. Comparator is also simple, XNOR is the one that compares two bits. Here only one bit processing is shown. If all the 4 bits are same, equal will be asserted. There are other tricky issues here. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 27

28 Data-path implementation (cont d) Tri-state logic utilize a third output state: no connection or float connect outputs together as long as only one is enabled open-collector (OC) gates can only output, not can be used to implement logical AND with only wires value_i Ci C2i C3i mux control value 4 C C2 C multiplexer 4 comparator mux control equal + oc equal tri-state driver (can disconnect from output) open-collector connection (zero whenever one connection is zero, one otherwise wired AND) To reduce the number of gates, we use tri-state logic and open-collector (OC) gates. The MUX becomes very slim thanks to the tri-state buffers. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 28

29 Tri-state gates The third value logic values:, don't care: X (must be or in real circuit!) third value or state: Z high impedance, infinite R, no connection Tri-state gates additional input output enable (OE) output values are,, and Z In when OE is high, the gate functions normally when OE is low, the gate is disconnected from wire at output allows more than one gate to be connected to the same output wire as long as only one has its output enabled at any one time (otherwise, sparks could fly) OE Out non-inverting tri-state buffer In OE Out X Z In OE Out We already know what is a tri-state gate. High impedance state is different from a don t care condition. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 29

30 Tri-state and multiplexing When using tri-state logic () make sure never more than one "driver" for a wire at any one time (pulling high and low at the same time can severely damage circuits) (2) make sure to only use value on wire when its being driven (using a floating value may cause failures) Using tri-state gates to implement an economical multiplexer Input F OE when Select is high Input is connected to F Input OE when Select is low Input is connected to F this is essentially a 2: mux Select X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 3

31 Open-collector gates and wired-and Open collector: another way to connect gate outputs to the same wire gate only has the ability to pull its output low it cannot actively drive the wire high (default pulled high through resistor) In normal transistor logic, the pull up resistor is inside The resistor is connected to voltage source X Z In normal or default transistor technologies, output can be actively pulled high or low. In open-collector gates, the output cannot be driven to a high voltage. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 3

32 Open-collector gates and wired-and Wired-AND can be implemented with open collector logic if A and B are "", output is actively pulled low if C and D are "", output is actively pulled low if one gate output is low and the other high, then low wins if both gate outputs are "", the wire value "floats", pulled high by resistor low to high transition usually slower than it would have been with a gate pulling high hence, the two NAND functions are ANDed together open-collector NAND gates with ouputs wired together using "wired-and" to form (AB)'(CD)' So the open-collector gates can resolve the bus fight (different output voltages can conflict) in a different way from the tri-state buffer. When a NAND gate with opencollector gate is high, it will float. So in this case, only when both NAND gates are generating s, F will be high (kind of an AND function). In summary, using opencollector gates remove the AND gate. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 32

33 Digital combination lock (new data-path) Decrease number of inputs Remove 3 code digits as inputs use code registers make them loadable from value need 3 load signal inputs (net gain in input (4*3) 3=9) could be done with 2 signals and decoder (ld, ld2, ld3, load none) ld ld2 ld3 value 4 C C2 C multiplexer 4 comparator mux control equal Instead of using additional wires for storing passwords (three numbers in order), we will reuse the input wires for pressing numbers. Load (ld) wires are kind of enable wires for FFs.. X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 33

34 Chapter summary FSM design understanding the problem generating state diagram communicating state machines Four case studies understand I/O behavior draw diagrams enumerate states for the "goal" expand with error conditions reuse states whenever possible X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 34

35 Final announcement Course feedback online This time, no password is needed Details will be posted on the web later X - Sequential Logic Case Studies Copyright 24, Gaetano Borriello and Randy H. Katz 35