5.14 Algorithmic State Machine (ASM) Charts

Transcription

1 5.4 Algorithmic State Machine (ASM) Charts An ASM chart is an alternative method for describing a state machine More directly shows the sequential steps of a state machine. Easier to understand input priority Less cluttered than a state transition graph (STG) Similar to software flow chart State State Output or Reg Op Decision Decision Output or Reg Op Chapter 5c Copyright 22 Greg Tumbush v.2

2 Tail Light Controller Example S_stop S_med rst brake Tail_Lite Tail_Lite brake accel brake=/ Tail_Lite= S_stop rst= accel = & brake= S_fast brake= accel S_slow S_fast brake accel = & brake= accel = & brake= S_slow brake=/ Tail_Lite= brake=/ Tail_Lite= brake=/ Tail_Lite= S_med accel = & brake= accel = & brake= brake Tail_Lite accel = & brake= accel Chapter 5c Copyright 22 Greg Tumbush v.2 2

3 5.5 Algorithmic State Machine and Datapath (ASMD) Charts Clarifies the design of a sequential machine by separating the design of it s datapath from the design of the controller Replace the symbol with annotations on path Output or Reg Op Separates the design of a datapath from it s controller clk reset Controller Control Signals Feedback Datapath Chapter 5c Copyright 22 Greg Tumbush v.2 3

4 Datapath Controller Design Steps. Determine the register operations of the datapath 2. Define an ASM chart of the controller 3. Annotate the ASM chart with the datapath operations 4. Annotate the ASM chart with the output signals 5. Design/Verify the controller 6. Design/Verify the datapath 7. Integrate the controller and datapath 8. Verify the integrated controller/datapath Chapter 5c Copyright 22 Greg Tumbush v.2 4

5 Pipeline Example Data 8 P[7:] 8 8 R[5:8] If input En=, P=Data, P=P Repeat once If input Ld =, R={P, P} Ld and En can assert simultaneously Clear P and P if Ld= and En= P[7:] R[7:] R 6. Determine the register operations of the datapath load_p_p, clear_p_p, load_r Chapter 5c Copyright 22 Greg Tumbush v.2 5

6 Pipeline Example S_idle S_idle S_idle Data 8 P[7:] 8 8 R[5:8] P[7:] R[7:] P<=Data P<=Data P<=P P<=P load_p_p rst rst En En S_ S_ Ld Ld rst En S_ S_full S_full S_full Ld R<={P,P} R<={P,P} load_r Chapter 5c Copyright 22 Greg Tumbush v.2 En En 2. Define an ASM chart of the controller 3. Annotate the ASM chart with the datapath operation 4. Annotate the ASM chart with the output signals R 6 En {P,P}<= {P,P}<= clear_p_p P<=Data P<=Data P<=P P<=P load_p_p 6

7 Pipeline Example - Block Diagram clk reset two_stage_pipe load_p_p Controller clear_p_p Datapath 6 R load_r Ld En Data 8 Chapter 5c Copyright 22 Greg Tumbush v.2 7

8 Pipeline Example 5) Design Controller `default_nettype none module controller(input wire clk, reset, input wire En, Ld, output reg load_p_p, clear_p_p, load_r); reg [:] current_state, next_state; parameter S_idle = 2'b; parameter S_ parameter S_full = 2'b; or En or Ld) begin load_p_p = 'b; clear_p_p = 'b; load_r = 'b; case (current_state) S_idle: begin if (En) begin next_state = S_; load_p_p = 'b; = 2'b; else begin //!En next_state = S_idle; // S_idle S_: begin next_state = S_full; load_p_p = 'b; Chapter 5c Copyright 22 Greg Tumbush v.2 8

9 Pipeline Example 5) Design Controller S_full: begin if (Ld) begin load_r = 'b; if (En) begin next_state = S_; load_p_p = 'b; else begin next_state = S_idle; clear_p_p = 'b; else next_state = S_full; default: next_state = S_idle; case // Current state registers clk or posedge reset) begin if (reset) current_state <= S_idle; else current_state <= next_state; module Chapter 5c Copyright 22 Greg Tumbush v.2 9

10 Pipeline Example 6) Design Datapath `default_nettype none module datapath(input wire clk, reset, input wire load_p_p, clear_p_p, load_r, input wire [7:] Data, output reg [5:] R); reg [7:] P, P; clk or posedge reset) begin if (reset) begin P <= 8'b; P <= 8'b; else if (clear_p_p) begin P <= 8'b; P <= 8'b; else if (load_p_p) begin P <= Data; P <= P; // datapath for R clk or posedge reset) begin if (reset) R <= 6'b; else if (load_r) R <= {P,P}; module Chapter 5c Copyright 22 Greg Tumbush v.2

11 Pipeline Example 7) Integrate CTRL/DP `default_nettype none module two_stage_pipe(input wire clk, reset, En, Ld, input wire [7:] Data, output wire [5:] R); wire load_p_p, clear_p_p, load_r; datapath datapath(.clk(clk),.reset(reset),.load_p_p(load_p_p),.clear_p_p(clear_p_p),.load_r(load_r),.data(data),.r(r) ); controller controller(.clk(clk),.reset(reset),.en(en),.ld(ld),.load_p_p(load_p_p),.clear_p_p(clear_p_p),.load_r(load_r) ); module Chapter 5c Copyright 22 Greg Tumbush v.2

12 Pipeline Example 8) Verify CTRL/DP `default_nettype none module two_stage_pipe_tb; reg clk, reset, En, Ld; reg [7:] Data; wire [5:] R; initial begin clk = 'b; forever # clk =!clk; initial begin En=; Ld=; Data=; reset = clk); reset = 'b; Data = 8'hA3; En = clk); En = ; Data = clk); clk); Ld=; // initial two_stage_pipe two_stage_pipe(.clk(clk),.reset(reset),.en(en),.ld(ld),.data(data),.r(r)); module Chapter 5c Copyright 22 Greg Tumbush v.2 2

13 Pipeline Example 8) Verify CTRL/DP Chapter 5c Copyright 22 Greg Tumbush v.2 3

14 Exercise Draw the ASMD chart for a circuit that loads a 4-bit word data_in into a register hold_reg when input load is asserted and determines if the word is odd-parity. If the value in register hold_reg is odd parity load the word into register correct. If the parity is incorrect load the word into register incorrect. Wait until input received is asserted before looking for another load input. Chapter 5c Copyright 22 Greg Tumbush v.2 4

15 Mechanical Switches Most (all?) mechanical switches will bounce. Vdd Push Button out 2ms out Chapter 5c Copyright 22 Greg Tumbush v.2 5

16 Why is bouncing a problem?. Will cause metastability if bounce occurs on a clock edge Vdd Push Button out D Q Q clk clk D Q 2. Will record numerous events Chapter 5c Copyright 22 Greg Tumbush v.2 6

17 Methods to Eliminate Bounce. RC debouncer 2. Nand latch 3. Synchronizer with a long cycle time 4. Counter Chapter 5c Copyright 22 Greg Tumbush v.2 7

18 RC Debouncer R R2 inv_in inv_out C Going from open to closed: C is discharged through R2. If bouncing occurs C charges through R+R2 to slow discharging. Going from closed to open: C is charged through R+R2. If bouncing occurs C discharges through R2 to slow charging. Chapter 5c Copyright 22 Greg Tumbush v.2 8

19 RC Debouncer - cont How to pick the inverter? TTL defines logic from -.8v. A logic- starts at 2.v. R R2 inv_in C inv_out Use an inverter with Schmitt Trigger inputs. These devices have no input range where the output is undefined. inv_in inv_out Schmitt Trigger inv_out Chapter 5c Copyright 22 Greg Tumbush v.2 9

20 Nand Latch Vdd Assumption: With a double pole switch once the arm leaves a terminal it does not return. It may bounce at new terminal A out B C Arm in upper position: A=, out= B=,C= Arm leaves A: A=, out stays at Arm in lower position: B=, C=, A=, out= Arm leaves B: B=, out stays at Arm in upper position: A=, out=, B=,C= Bouncing has no effect Vdd Chapter 5c Copyright 22 Greg Tumbush v.2 2

21 Metastability Occurs if a FF's setup/hold time requirement is not met Output will be between and momentarily Output may change state, might not Metastable state State_ State_ D D Q Q clk clk D Q M. Ciletti, Advanced Digital Design with Verilog HDL, Prentice Hall, 22 Chapter 5c Copyright 22 Greg Tumbush v.2 2

22 Metastability- 4 possibilities clk D Q clk D Q clk D Q clk D Q Chapter 5c Copyright 22 Greg Tumbush v.2 22

23 Eliminating Bounce with a Synchronizer Cycle time (i.e. clock period) must be > total bounce time async_in q D Q D Q sync_out clk clk async_in q sync_out Chapter 5c Copyright 22 Greg Tumbush v.2 23

24 Eliminating Bounce with a Counter Increment a counter anytime async_in!= sync_out Clear the counter anytime async_in == sync_out When counter = MAX sync_out =!sync_out Critical constraint: How long will bounce stay at: for a low going input for a high going input 3ms 3ms async_in ms ms sync_out Chapter 5c Copyright 22 Greg Tumbush v.2 24

25 Eliminating Bounce with a Counter (cont) ms ms async_ in counter clr cnt clr cnt clr cnt clr cnt=max clr cnt clr cnt clr cnt clr cnt=max clr sync_out For MHz clock and a 6-bit counter, input must be stable for 6 max_ count 2 to detect a change 6.5ms 7 frequency Chapter 5c Copyright 22 Greg Tumbush v.2 25

26 Debounce Exercise Given the following timing diagram of a bouncing input determine:. The min clock frequency if a synchronizer is used to debounce input async_in 2. The clock frequency and counter size if a counter is used to debounce input async_in async_in 3ms 3ms ms ms Chapter 5c Copyright 22 Greg Tumbush v.2 26

27 Synchronizer for Asynchronous inputs clk async_in q async_in q D Q D Q sync_out sync_out clk clk async_in q sync_out Chapter 5c Copyright 22 Greg Tumbush v.2 27

28 More compiler directives `timescale time_unit / time_precision defines the time units and the precision `define is used to define a text macro for substitution Compiler directives are in force until another directive overrides it. Examples: `timescale us/ns `define HALF_PERIOD_5KHZ # initial begin clk_5khz = 'b; forever `HALF_PERIOD_5KHZ clk_5khz = ~ clk_5khz; Chapter 5c Copyright 22 Greg Tumbush v.2 28