EECS 373 Midterm Winter 2013

Transcription

1 EECS 373 Midterm Winter 2013 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Page Points 2 /15 3 /20 4 /12 5 /13 8 /10 9 /15 10 /15 Total /100 NOTES: 1. Closed book/notes. 2. There are 10 pages including this one. 3. Calculators are allowed, but no PDAs, Portables, Cell phones, etc. 4. Don t spend too much time on any one problem. 5. You have about 80 minutes for the exam. 6. Be sure to show work and explain what you ve done when asked to do so. Getting partial credit without showing work will be rare. 7. Throughout the exam standard logic gates means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Page 1 of 10

2 1. Fill-in-the-blank or circle the best answer. [15 points, -3 per wrong or blank answer, minimum 0] a) A 10 MHz clock with a duty cycle of 40% is high for ns per cycle. b) When an ISR A can interrupt another (running) ISR B, A is said to be able to preempt / override / nest / remove B. c) Set-up and/or hold time matter in embedded systems primarily because: the hold time impacts the processor s clock period. the set-up time impacts the processor s ability to use timers. inputs not synchronized to our local clock run the risk of violating them. they have a significant impact on interrupt latency. d) One interesting feature of our ISA is that: R11 is used as a dedicated frame pointer there is no way to use an immediate with more than 4 bits many instruction encodings can only use registers R0-R7. e) In the following text, the blank should be replaced with unified / global / V6T2 / function. Two slightly different syntaxes are supported for ARM and THUMB instructions. The default, divided, uses the old style where ARM and THUMB instructions had their own, separate syntaxes. The new, syntax, which can be selected via the.syntax directive, and has the following main features: Immediate operands do not require a # prefix. The IT instruction may appear, and if it does it is validated against subsequent conditional affixes. In ARM mode it does not generate machine code, in THUMB mode it does. For ARM instructions the conditional affixes always appear at the end of the instruction. For THUMB instructions conditional affixes can be used, but only inside the scope of an IT instruction. f) Say we were using an APB bus that had 20 bits for the address and 32 bits for the data. If the bus were running at 10MHz, the most bandwidth you could expect to get over the bus would be about 10 / 20 / 32 / 40 / 64 Mbytes/sec. Page 2 of 10

3 2. Write an ARM assembly language procedure that implements the following C function in an EABIcompliant manner and conforms to the following signature. Clearly comment your code so we can figure out what you are doing and what value each register holds. Poorly commented/unclear code will get points removed. [20 points] uint32 XYbob(uint32 x, uint32 y, uint32 bob[]) { uint32 mary[10]; } fill(mary,x,y); // function moves data into the array mary if(bob[x]>=mary[y]) return(x); else return(y); Page 3 of 10

4 3. Consider the ARM assembly found below. Assume that r3=0x88aaccdd, r1=0x , and all other registers and memory locations are initialized to zero. You should assume the processor is in little-endian mode. str r3, [r1],1 ldrsh r5, [r1,1]! orr r5, r5, 0xF strh r3, [r1,-1] ldr r3, [r1] What are the values of these registers? You must write your answers as 8-digit hex numbers if you wish to receive credit! [12 points, 4 each, no partial credit] r1= r3= r5= Page 4 of 10

5 4. Briefly explain what the volatile keyword in C does and why it is necessary, i.e. what could happen if you forget to use it? [8 points] 5. Briefly explain why having a capture option on a timer is useful. [5 points] Page 5 of 10

6 Anemometer design Your task is to design the measurement system for a hand-held anemometer. The device measures wind speed with a traditional rotating cup system. Wind speed is determined by measuring the rotation period, scaling and displaying accordingly. You will likely find it helpful to read the rest of the exam before solving any of the following parts. To make the measurement, you have at your disposal a simplified Smart Fusion kit and a hardware timer. Interface to the APB bus The kit has the following APB3 bus interface. The signal names are shown in bold. The ABP3 bus signals follow APB3 timing and protocol. Read and write cycles are provided on the next page. PSEL is configured to be 1 when memory locations 0x x are accessed. SmartFusion Level Sensitive Interrupt: INT APB Write Data: PWDATA (32 bits) APB Read Data: PRDATA (32 bits) APB Peripheral Write: PWRITE Peripheral Address: PADDR (8 bits) Peripheral Select: PSEL Bus Clock: PCLK Bus Ready: PREADY As shown, this system has a single interrupt that can be generated. It is level-sensitive and is named INT. Page 6 of 10

7 Hardware Timer The hardware timer will become the value on TDI if TWE is high on the positive edge of the timer clock. Otherwise the counter will increment every cycle. If the counter reaches its maximum value it wraps around to zero (i.e. it is a modulo counter). The current value of the timer is always available on TDO. Timer Timer Data In: TDI (32 bits) Timer Data Out: TDO (32 bits) Timer Write Enable: TWE Timer Clock: TC APB Timing diagram The following diagrams are provided as a reminder of the APB timing with no wait states. ABP3 Read Timing ABP3 Write Timing Page 7 of 10

8 Part 1: Hardware Timer APB3 Bus Interface (10 points) Provide a hardware interface between the SmartFusion APB3 bus and the hardware timer to allow the SmartFusion to read and write the counter. Assume the timer s counter register is at address 0x (and only that address). You may use standard gates such as ANDs, ORs, NOTs (as well as standard bubbles). Be sure to show all connections. You may use GND and VCC to indicate a logical 0 and 1 respectively. You may not use Boolean or Verilog expressions. You will lose points for having unneeded logic. Note: we have put all the APB connections on the left and all the Timer connections on the right. This means inputs and outputs are intermixed, be sure you are driving all outputs! [15 points] PWDATA[31:0] TDI[31:0] PRDATA[31:0] TDO[31:0] PWRITE PENABLE TWE PSEL PADDR[7:0] PCLK TC PREADY Page 8 of 10

9 Part 2: Anemometer Interrupt Hardware Interface (15 points) The anemometer provides a high pulse (signal name PULSE) that is several clock (PCLK) cycles wide and is not synchronized to the APB clock. We wish to use this signal to generate an interrupt and then use the counter to time the period of each anemometer rotation. The only interrupt line available on your processor is level sensitive and is active high. This means it will interrupt as long as it remains high. Design logic using standard gates and D flip-flops that will provide the level-sensitive interrupt when PULSE goes high. Recall you have to hold a level-sensitive interrupt true until it is cleared by the interrupt service return. o One D flip-flop is provided, though you may use additional ones as needed. Also, provide logic that will clear the interrupt when a write to memory address 0x (and only that address) occurs. PULSE PCLK PWDATA[31:0] D flip-flop D Q C Reset INT PWRITE PENABLE PADDR[7:0] PSEL Page 9 of 10

10 Part 3: Interrupt Service Routine (15 points) Write an interrupt service routine in C called anemometer_interupt that will calculate and display the wind speed by reading the time of a rotation, scaling and then displaying the result using your hardware designed above. Assume that you have a function called scale that will convert the time of rotation to KPH. Scale accepts time per rotation in microseconds. Assume that you have another function called display that accepts KPH and provides display. It is acceptable if the first speed value is incorrect. All subsequent values should be correct. Assume the APB bus runs at 1 MHz. Function Prototypes: (void) display (int kph) (int kph)scale (int ms) Providing comments may improve your chance for partial credit. Page 10 of 10