Design of Embedded DSP Processors Unit 2: Design basics. 9/11/2017 Unit 2 of TSEA H1 1

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1 Design of Embedded DSP Processors Unit 2: Design basics 9/11/2017 Unit 2 of TSEA H1 1

2 ASIP/ASIC design flow We need to have the flow in mind, so that we will know what we are talking about in later lectures 9/11/2017 Unit 2 of TSEA H1 2

3 ASIP design flow (detailed) Understand Application, Source code analysis, Kernel extraction & transform Parallel architecture selection (pipeline, data parallel, ILP, and task parallel) Design AIS & ASM coding tools, Benchmark with sufficient redundants Change ISA? No Satisfied? Microarchitecture design (for datapath, parallel data access, and control path) Yes ASIP Verification, VLSI coding, critical path fiting, and backend design 2017/9/11 Unit 2 of TSEA H1 3

4 Understand application Understand Application, Source code analysis, Kernel extraction & transform Parallel architecture selection (for pipeline, data, ILP, and task parallel) Design AIS & ASM coding tools, Benchmark with sufficient redundants Change ISA? No Satisfied? Yes Microarchitecture design (for datapath, parallel data access, and control path) ASIP Verification, VLSI coding, critical path fiting, and backend design 1. The goal: Understand the computing cost /features, storage cost / features, data access cost / features, & control cost / features. 2. Method: Do not need understanding WHY, need to understand HOW Reading books and codes 3. DOC Release: A spec to expose Coverage and scope Inputs and outputs Algorithm (set) behaviors Computing and access cost / features 2017/9/11 Unit 2 of TSEA H1 4

5 Kernel code extraction Understand Application, Source code analysis, Kernel extraction & transform Parallel architecture selection (for pipeline, data, ILP, and task parallel) Design AIS & ASM coding tools, Benchmark with sufficient redundants Change ISA? No Satisfied? Yes Microarchitecture design (for datapath, parallel data access, and control path) ASIP Verification, VLSI coding, critical path fiting, and backend design 1. Principle (DSP codes) Code = kernels + top FSM + config 90% - 10% code locality rule 2. The goal: Collect innermost loops and plan for acceleration 3. Method Code profiling Reading and extract the innermost loops Guiding to design for acceleration 4. Release kernel list Classify kernels (a. data parallel, b. task parallel, c. cannot be parallel) 2017/9/11 Unit 2 of TSEA H1 5

6 Select an architecture template Understand Application, Source code analysis, Kernel extraction & transform Parallel architecture selection (for pipeline, data, ILP, and task parallel) Design AIS & ASM coding tools, Benchmark with sufficient redundants Change ISA? No Satisfied? Yes Microarchitecture design (for datapath, parallel data access, and control path) 1. The goal: To find an architecture and instruction set for both specific requirements and essential software ecological environment 2. Method: Popular instruction set extension with architectural license, or use Synopsys ASIP designer 3. Release: Architecture ASM proposal, SW development flow (proven by SW designers). ASIP Verification, VLSI coding, critical path fiting, and backend design 2017/9/11 Unit 2 of TSEA H1 6

7 AIS Design for algorithm acceleration Understand Application, Source code analysis, Kernel extraction & transform Parallel architecture selection (for pipeline, data, ILP, and task parallel) Design AIS & ASM coding tools, Benchmark with sufficient redundants Change ISA? No Satisfied? Yes Microarchitecture design (for datapath, parallel data access, and control path) ASIP Verification, VLSI coding, critical path fiting, and backend design 1. The goal: Design ASM instruction set based on the understanding on SIMD / task level parallel analysis 2. Method Design for acceleration: Instruction fusion and configurable magic blocks ASIP design: Decomposate and Map functions to instruction set ASIC module design: Drectly map functions on circuit Trade off performance-and-cost 3. Release Datapath HW design specification 2017/9/11 Unit 2 of TSEA H1 7

8 Design for custom data type Understand Application, Source code analysis, Kernel extraction & transform Parallel architecture selection (for pipeline, data, ILP, and task parallel) Design AIS & ASM coding tools, Benchmark with sufficient redundants Change ISA? No Satisfied? Yes Microarchitecture design (for datapath, parallel data access, and control path) ASIP Verification, VLSI coding, critical path fiting, and backend design 1. Goal: custom data types to speed up, and to reduce cost & power 2. Method Real and complex data Fixed point (integer, fractional, signed, unsigned) and custom floating point Trade-off precision (quality) and cost 3. Release Internal precision for quality iterations Native precision to reduce memory cost Data precisions for native/iteration Corner cases as extra design cost 2017/9/11 Unit 2 of TSEA H1 8

9 Design for data access and memories Understand Application, Source code analysis, Kernel extraction & transform Parallel architecture selection (for pipeline, data, ILP, and task parallel) Design AIS & ASM coding tools, Benchmark with sufficient redundants Change ISA? No Satisfied? Yes Microarchitecture design (for datapath, parallel data access, and control path) ASIP Verification, VLSI coding, critical path fiting, and backend design 1. The goal: Design for data access 2. Method Expose (get) requirements for data access Distribute complexities between Main memory and local memories Local memories and datapath ports Add data access operations into ASM Design for data access hardware 3. Release Data access requirements and compiling/ programming requirements Specification for addressing (function) 2017/9/11 Unit 2 of TSEA H1 9

10 AIS Design for control functions Understand Application, Source code analysis, Kernel extraction & transform Parallel architecture selection (for pipeline, data, ILP, and task parallel) Design AIS & ASM coding tools, Benchmark with sufficient redundants Change ISA? No Satisfied? Yes Microarchitecture design (for datapath, parallel data access, and control path) ASIP Verification, VLSI coding, critical path fiting, and backend design 1. The goal: control path design 2. Method Plan pipeline for data access and datapath Plan for all branchs, HW loops, and design for all pipeline tables Instruction coding (ASM to BIN) 3. Release Control path HW specification HW microarchitecture design spec ASM user s manual 2017/9/11 Unit 2 of TSEA H1 10

11 Benchmark kernels & Applications Understand Application, Source code analysis, Kernel extraction & transform Parallel architecture selection (for pipeline, data, ILP, and task parallel) Design AIS & ASM coding tools, Benchmark with sufficient redundants Change ISA? No Satisfied? Yes Microarchitecture design (for datapath, parallel data access, and control path) ASIP Verification, VLSI coding, critical path fiting, and backend design 1. The goal: measure the performance of the designed ASIP instruction set 2. Method BDTI / EEMBC benchmarks Do not use SPEC Standard Performance Evaluation Corporation offered bench Run other kernels Compiled (compiler quality) Hand coded (hardware quality) Run applications 3. Release: to prove the quality of The ISA and Compiler design 2017/9/11 Unit 2 of TSEA H1 11

12 Quality design for Fixed point computing Finite precision HW 9/11/2017 Unit 2 of TSEA H1 12

13 Fixed poing HW design challenge Fixed point HW design is challenging and rewarding Rewarding: Low silicon cost, high performanc Challenging: MSB part: limited dynamic range and LSB part: quantization error LSB part: Round up before truncation MSB part: Guard to avoid overflow, saturate to handle overflow for real time computing 9/11/2017 Unit 3 of TSEA H1 13

14 Fixed point numerical representation Why fixed point (Important) Easy to implement data path hardware (HW) Low HW cost (low chip area), low power High speed (short physical critical path) Important! the precision must be acceptable Why not fixed point (sometimes) Cannot separate dynamic range and precision High firmware design skills & FW design cost 08/19/09 Unit 2 of TSEA H1 14

15 Definitions Definition 1: Truncation: To convert a longer numerical format to a shorter one by simple cutting off bits at the LSB part. Definition 2: Quantization error The numerical error introduced after truncation (a problem on result) 08/19/09 Unit 2 of TSEA H1 15

16 Truncation and rounding Truncation on data (α) without sign bit from c-bit data to b-bit data (c > b) we have: x b i = 1 c = i 2 i + i 2 i = Q T x + i = b + 1 E T will be cut off Quantization error of value x is E T =Q T [x] - x. MAX {E T } is - (2 -b -2 -c ) -2 -b =. Definition of rounding: E T 08/19/09 Unit 2 of TSEA H1 16

17 A rounding example Round Arithmetic Example: Round 8 bits to 4 bits Sign bit Before round: 8 bits A7 A6 A5 A4 A3 A2 A1 A0 Sign bit After round: 4 bits Round to nearest b[3:0] = a[7:4] + {000, a[3]} b7 b6 b5 b4 08/19/09 Unit 2 of TSEA H1 17

18 Avoid overflow: guard & saturation Overflow: if the result of a calculation (X) is not in the range -2 -N-1 X < 2N-1 Common reasons of overflow: When the result is too large (or small) Shift out useful bits on the left side Too many iterative accumulations 08/19/09 Unit 2 of TSEA H1 18

19 Manage Overflow: scale down input Arithmetic right shift Precision is lower Larger quantization errors When shall we scale down Iteration loop is too long Low requirement on precision No other choice 08/19/09 Unit 2 of TSEA H1 19

20 08/19/09 Unit 2 of TSEA H1 20 Add guard bits When accumulation is needed, guard bits are needed. Example for an FIR filter: y k n x max h k m m = both the scaling factor or the guard factor: f scaling 1 h k m m = = f guarding h k m m = =

21 Manage Overflow: saturation Saturation: after executing an algorithm if(result 1){ final_result = 1-2 -n+1 }else if(result <-1) { final_result = -1 }else{ final_result = result // no overflow } // fractional data type Do it after an iterative accumulation Do not do it during an iteration! Discussion: compare to exception 08/19/09 Unit 2 of TSEA H1 21

22 Manage Overflow: an example An example: extension of 4 guard bits for accumulation and saturation Sign bit Before guard: 4-bit OPA a 3 a 2 a 1 a 0 Sign bit 4-bit OPB b 3 b 2 b 1 b 0 After guard: 8-bit Sign bit Sign bit ga 4 ga 3 ga 2 ga 1 a 3 a 2 a 1 a 0 gb 4 gb 3 gb 2 gb 1 b 3 b 2 b 1 b 0 guards=a 3 Accumulator guards=b 3 8-bit full adder + Accumulator register Data could be out of range during accumulation gc 4 gc 3 gc 2 gc 1 c 3 c 2 c 1 c 0 iteration After accumulation Dynamic range The final result is correct Saturation d 3 d 2 d 1 d 0 After saturation, the final result is 4-bits 08/19/09 Unit 2 of TSEA26 22

23 Fixed poing HW design review Fixed point HW design is challenging and rewarding Rewarding: Low silicon cost, high performanc Challenging: MSB part: limited dynamic range and LSB part: quantization error LSB part: Round up before truncation MSB part: Guard to avoid overflow, saturate to handle overflow for real time computing 9/11/2017 Unit 3 of TSEA H1 23

24 Instruction set design 9/11/2017 Unit 2 of TSEA H1 24

25 From Junior to Senior Step 1: To design a simple instruction set with only basic instructions for function coverage Move data, arithmetic and logic, flow control Step 2: To improve the simple instruction set by adding instructions for accelerations SW-HW co-design: what, why, and how To find the distance between the expected and the current benchmark scores Add instructions for (1). more functions (coverage) and (2). for accelerations 9/11/2017 Unit 2 of TSEA H1 25

26 What is a simplest instruction set ALU for data manipulation from memory D in memory = A in memory + B in memory D in memory = A in memory - B in memory What are problems: 3 memories in parallel (silicon cost) Long time to access (time cost) Memory independent core IP design! Using register file as computing buffer 9/11/2017 Unit 2 of TSEA H1 26

27 What is a simplest instruction set LOAD data from memory to register A LOAD data from memory to register B Register D = Register A + Register B STORE data in register D to memory RISC machine is introduced: Load / store to/from register file (computing buffer) Usually one load/store v.s. multi ALU operations ALU operation:+, -, *, shift, and, or, xor, not; not for /, %, sine, cosine, logarithm, exp. Why? Load store operations: Load / store R M(address) Address computing (direct, indirect, post/pre ++, --) 9/11/2017 Unit 2 of TSEA H1 27

28 Classify the simplest Instruction set Instruction group /type Operands Operations Mathematical description Flags CC Load, store, and move Register name and memory addressing Moving data DST (ADR) <= SRC (ADR) No flag 1 ALU instructions REG names or immediate data Arithmetic logic/shift operations DST (ADR) <= OA op OB ALU Flag 1 Flow control Way to get target address Jump taken decision If condition true PC <= target address No flag 1 or 3 9/11/2017 Unit 2 of TSEA H1 28

29 Move-load-store instructions Mnem Operand Description Operation CC Load Rd, DA Load data from memory 0/1 Store DA, Rs Store data to memory 0/1 move Rd, Rs Move between two registers move Rd, K Move immediate data to a register Rd DM(DA) 1 DM(DA) Rs 1 Rd Rs 1 Rd immediate 1 9/11/2017 Unit 2 of TSEA H1 29

30 Basic Arithmetic Instructions Mnem Operand Description Operation Flags ADD Rd, Rr Add Rd Ra + Rb Z,N,V SUB Rd, Rr Subtract Rd Ra - Rb Z,N,V ABS Rd, Rr Absolute operation Rd ABS(Ra) Z,N,V INC Rd Increment Rd Ra + 1 Z,N,V DEC Rd Decrement Rd Ra - 1 Z,N,V MPL A, Rd, Rr Multiplication A Ra Rb Z,N,V MAC A, Rd, Rr Multiplication and accumulation RND Rd, A Round, saturate, and truncate CAC A Clear an accumulator A A + Ra Rb Rd Saturate(Round(A)) A 0 Z,N,V Z,N,V Z,N,V 9/11/2017 Unit 2 of TSEA H1 30

31 Logic and Shift Operations Mnem Operand Description Operation Flags AND Ra, Rb A logic-and B Rd Ra and Rb C, Z OR Ra, Rb A logic-or B Rd Ra or Rb C, Z NOT Ra, Rb Invert A Rd INV (Ra) C, Z XOR Ra, Rb A logic-xor B Rd Ra xor Rb C, Z LS Ra, Rb Logic left shift Rd Ra left shifted by Rb [3:0] RS Ra, Rb Logic right shift Rd Ra right shifted by Rb [3:0] C, Z C, Z 9/11/2017 Unit 2 of TSEA H1 31

32 Program flow control instructions Description Conditions Flags meet Jump when Less than < N=1 Jump when Less than or Equal to <= N=1 or Z=1 Jump when Equal to == Z=1 Jump when Greater than or Equal to >= N=0 Jump when Greater than > N=0 and Z=0 Jump when Not Equal to!= Z=0 Unconditional jump Call, push return address into stack Return to the stacked address 9/11/2017 Unit 2 of TSEA H1 32

33 Benchmarking the instruction set 9/11/2017 Unit 2 of TSEA H1 33

34 What is benchmark DSP benchmarking gets cycle cost and code size consumed by a DSP algorithm with single-precision data. Convention of DSP benchmarking round is required before moving long data from an accumulation register to a general register 9/11/2017 Unit 2 of TSEA H1 34

35 What to benchmark Algorithm Kernel Block transfer Single FIR Frame FIR IIR 16-bit division Vector add Windowing Vector Max DCT 256p complex FFT Description Transfer a data block from one memory to another memory N-tap FIR filter running one data sample N-tap FIR filter running K data samples Biquad IIR (2nd order IIR) running one data sample A positive 16 bit value divided by another positive 16 bit value C[i] = A[i] + B[i], i=0 N-1 (not included in this chapter) C[i] = A[i] * B[i], i=0 N-1 (not included in this chapter) R <= MAX { A[i]}, i=0 N-1 8X8 2D Discrete Cosine Transform 256 point FFT including all computing and addressing 9/11/2017 Unit 2 of TSEA H1 35

36 How to benchmark BDTI benchmarking convention It measures the execution time (cycle cost), the code size, and the cost of data memories. The cycle cost = prologue + Kernel + epilogue Prologue: preparing and starting a program, Epilogue: terminating a program Kernel: the part of the algorithm 9/11/2017 Unit 2 of TSEA H1 36

37 Example: Block Transfer C-code: DM1 (SEG: 0 to 39) -> DM1 (SEG: 0 to 39) Assembly code Comparing the cost: Extra jump cost Processor Algorithm Total cycle cost Junior BT TSMD 47 4 Pro-epilogue cycle cost Kernel cycle cost Total code cost Code for proepilogue DM cost 9/11/2017 Unit 2 of TSEA H1 37

38 Example: Single sample FIR C-code: 16-tap FIR Assembly code Comparing the cost: Extra jump cost, modulo addressing Processor Algorithm Total cycle cost Kernel cycle cost Total code cost Junior 16-tapFIR 192 TSMD 16-tapFIR /11/2017 Unit 2 of TSEA H1 38

39 HW/SW co-design for an ASIP ASIP requirement specification Early manual partition according to application profiling Instruction set specification Implement the function as an instruction Implement the function as a subroutine Processor architecture specification Assembly instruction set simulator Microarchitecture design Benchmarking of instruction set Implement the function as an instruction Implement the function as a subroutine Design for HW acceleration Application SW implementation Processor HW implementation ASIP Integration, final function verification and performance validation 9/11/2017 Unit 2 of TSEA H1 39

40 Concepts Finite precision Skills Review on Unit 2 System understanding Quantization error Guard Saturation Rounding Plan HW schematic The order to run G/S/R MAC: MUL and ACC MAC HW is essential Reuse skill Memory and data access Program flow control Two memories for D and C Execution on memory data Modulo addressing HW iterative loop control Pipeline functional fusion Pipeline I-decoders FW coding When and where to saturate and round MAC result data dependency Carefully and statically allocate data Efficient coding for innermost loop codes 9/11/2017 Unit 2 of TSEA H1 40

41 Self reading after the lecture Guard/saturation/round in chapter 2 Quick reading through chapter 4, 9 Think about: Why do we need two data memories Why do we need HW for iterative computing How can we minimize extra data access cost during convolution 9/11/2017 Unit 2 of TSEA H1 41

42 Exciting time now! Let us discuss Whatever you want to discuss and related to HW You will have the chance after each lecture (Fö), do take the chance! Prepare your Qs for the next time 9/11/2017 Unit 2 of TSEA H1 42

43 LOGO Welcome to ask any questions you want to I can answer Or discuss together I want to know what you want Dake Liu, Room 556 coridoor B, Hus-B, phone , dake.liu@liu.se